| 105 |
105 |
#define ACPI_CPU_NOTIFY_PERF_STATES 0x80 /* _PSS changed. */
|
| 106 |
106 |
#define ACPI_CPU_NOTIFY_CX_STATES 0x81 /* _CST changed. */
|
| 107 |
107 |
|
| 108 |
|
#define CPU_QUIRK_NO_C3 0x0001 /* C3-type states are not usable. */
|
| 109 |
|
#define CPU_QUIRK_NO_THROTTLE 0x0002 /* Throttling is not usable. */
|
|
108 |
#define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
|
|
109 |
#define CPU_QUIRK_NO_THROTTLE (1<<1) /* Throttling is not usable. */
|
|
110 |
#define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
|
| 110 |
111 |
|
| 111 |
112 |
#define PCI_VENDOR_INTEL 0x8086
|
| 112 |
113 |
#define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
|
| ... | ... | |
| 474 |
475 |
|
| 475 |
476 |
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
|
| 476 |
477 |
|
| 477 |
|
/* Bus mastering arbitration control is needed for C3. */
|
|
478 |
/*
|
|
479 |
* Bus mastering arbitration control is needed to keep caches coherent
|
|
480 |
* while sleeping in C3. If it's not present but a working flush cache
|
|
481 |
* instruction is present, flush the caches before entering C3 instead.
|
|
482 |
* Otherwise, just disable C3 completely.
|
|
483 |
*/
|
| 478 |
484 |
if (AcpiGbl_FADT->V1_Pm2CntBlk == 0 || AcpiGbl_FADT->Pm2CntLen == 0) {
|
| 479 |
|
cpu_quirks |= CPU_QUIRK_NO_C3;
|
| 480 |
|
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
| 481 |
|
"acpi_cpu%d: No BM control, C3 disabled\n",
|
| 482 |
|
device_get_unit(sc->cpu_dev)));
|
|
485 |
if (AcpiGbl_FADT->WbInvd && AcpiGbl_FADT->WbInvdFlush == 0) {
|
|
486 |
cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
|
|
487 |
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
|
488 |
"acpi_cpu%d: no BM control, using flush cache method\n",
|
|
489 |
device_get_unit(sc->cpu_dev)));
|
|
490 |
} else {
|
|
491 |
cpu_quirks |= CPU_QUIRK_NO_C3;
|
|
492 |
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
|
493 |
"acpi_cpu%d: no BM control, C3 not available\n",
|
|
494 |
device_get_unit(sc->cpu_dev)));
|
|
495 |
}
|
| 483 |
496 |
}
|
| 484 |
497 |
|
| 485 |
498 |
/*
|
| ... | ... | |
| 922 |
935 |
* driver polling for new devices keeps this bit set all the
|
| 923 |
936 |
* time if USB is loaded.
|
| 924 |
937 |
*/
|
| 925 |
|
AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active,
|
| 926 |
|
ACPI_MTX_DO_NOT_LOCK);
|
| 927 |
|
if (bm_active != 0) {
|
| 928 |
|
AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1,
|
| 929 |
|
ACPI_MTX_DO_NOT_LOCK);
|
| 930 |
|
cx_next_idx = min(cx_next_idx, cpu_non_c3);
|
|
938 |
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
|
|
939 |
AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active,
|
|
940 |
ACPI_MTX_DO_NOT_LOCK);
|
|
941 |
if (bm_active != 0) {
|
|
942 |
AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1,
|
|
943 |
ACPI_MTX_DO_NOT_LOCK);
|
|
944 |
cx_next_idx = min(cx_next_idx, cpu_non_c3);
|
|
945 |
}
|
| 931 |
946 |
}
|
| 932 |
947 |
|
| 933 |
948 |
/* Select the next state and update statistics. */
|
| ... | ... | |
| 946 |
961 |
return;
|
| 947 |
962 |
}
|
| 948 |
963 |
|
| 949 |
|
/* For C3, disable bus master arbitration and enable bus master wake. */
|
|
964 |
/*
|
|
965 |
* For C3, disable bus master arbitration and enable bus master wake
|
|
966 |
* if BM control is available, otherwise flush the CPU cache.
|
|
967 |
*/
|
| 950 |
968 |
if (cx_next->type == ACPI_STATE_C3) {
|
| 951 |
|
AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK);
|
| 952 |
|
AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1, ACPI_MTX_DO_NOT_LOCK);
|
|
969 |
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
|
|
970 |
AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK);
|
|
971 |
AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1,
|
|
972 |
ACPI_MTX_DO_NOT_LOCK);
|
|
973 |
} else
|
|
974 |
ACPI_FLUSH_CPU_CACHE();
|
| 953 |
975 |
}
|
| 954 |
976 |
|
| 955 |
977 |
/*
|
| ... | ... | |
| 971 |
993 |
AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT->XPmTmrBlk);
|
| 972 |
994 |
|
| 973 |
995 |
/* Enable bus master arbitration and disable bus master wakeup. */
|
| 974 |
|
if (cx_next->type == ACPI_STATE_C3) {
|
|
996 |
if (cx_next->type == ACPI_STATE_C3 &&
|
|
997 |
(cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
|
| 975 |
998 |
AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0, ACPI_MTX_DO_NOT_LOCK);
|
| 976 |
999 |
AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0, ACPI_MTX_DO_NOT_LOCK);
|
| 977 |
1000 |
}
|
| ... | ... | |
| 1035 |
1058 |
{
|
| 1036 |
1059 |
|
| 1037 |
1060 |
/*
|
| 1038 |
|
* C3 is not supported on multiple CPUs since this would require
|
| 1039 |
|
* flushing all caches which is currently too expensive.
|
|
1061 |
* C3 on multiple CPUs requires using the expensive flush cache
|
|
1062 |
* instruction.
|
| 1040 |
1063 |
*/
|
| 1041 |
1064 |
if (ncpus > 1)
|
| 1042 |
|
cpu_quirks |= CPU_QUIRK_NO_C3;
|
|
1065 |
cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
|
| 1043 |
1066 |
|
| 1044 |
1067 |
#ifdef notyet
|
| 1045 |
1068 |
/* Look for various quirks of the PIIX4 part. */
|