rgephy.diff

dragonfly, 12/23/2005 09:22 PM

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sys/conf/files 23 Dec 2005 14:57:24 -0000
271 271
dev/netif/mii_layer/lxtphy.c   optional miibus
272 272
dev/netif/mii_layer/qsphy.c        optional miibus
273 273
dev/netif/mii_layer/acphy.c        optional miibus
274
dev/netif/mii_layer/rgephy.c   optional miibus
274 275
dev/netif/mii_layer/ruephy.c   optional miibus
275 276
dev/netif/mii_layer/miibus_if.m        optional miibus
276 277
dev/raid/mlx/mlx_disk.c        optional mlx
sys/dev/netif/mii_layer/Makefile 23 Dec 2005 15:03:07 -0000
6 6
SRCS   += miibus_if.h device_if.h miibus_if.c e1000phy.c exphy.c nsphy.c
7 7
SRCS   += mlphy.c tlphy.c rlphy.c amphy.c dcphy.c pnphy.c nsgphy.c
8 8
SRCS   += pnaphy.c brgphy.c xmphy.c inphy.c lxtphy.c qsphy.c acphy.c
9
SRCS   += ruephy.c nvphy.c
9
SRCS   += rgephy.c ruephy.c nvphy.c
10 10

  
11 11
.include "./Makefile.miidevs"
12 12

  
sys/dev/netif/mii_layer/miidevs 23 Dec 2005 20:43:43 -0000
91 91
/* Don't know what's going on here. */
92 92
oui xxDAVICOM          0x006040    Davicom Semiconductor
93 93

  
94
/* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */
95
oui xxREALTEK          0x000732
94 96

  
95 97
/*
96 98
 * List of known models.  Grouped by oui.
......
144 146

  
145 147
/* RealTek Semiconductor PHYs */
146 148
model REALTEK RTL8201L     0x0020 RTL8201L 10/100 media interface
149
model xxREALTEK RTL8169S       0x0011 RTL8169S/8110S media interface
147 150

  
148 151
/* Seeq PHYs */
149 152
model xxSEEQ 80220     0x0003 Seeq 80220 10/100 media interface
sys/dev/netif/mii_layer/miidevs.h 23 Dec 2005 20:45:34 -0000
1
/* $DragonFly: src/sys/dev/netif/mii_layer/miidevs.h,v 1.5 2004/02/10 21:14:14 hmp Exp $   */
1
/* $DragonFly$ */
2 2

  
3 3
/*
4 4
 * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
5 5
 *
6 6
 * generated from:
7
 * DragonFly: src/sys/dev/netif/mii_layer/miidevs,v 1.4 2004/02/09 16:41:33 hmp Exp 
7
 * DragonFly: src/sys/dev/netif/mii_layer/miidevs,v 1.5 2004/02/10 21:14:14 hmp Exp 
8 8
 */
9 9
/* $FreeBSD: src/sys/dev/mii/miidevs,v 1.4.2.13 2003/07/22 02:12:55 ps Exp $ */
10 10
/*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
......
98 98
/* Don't know what's going on here. */
99 99
#define    MII_OUI_xxDAVICOM   0x006040    /* Davicom Semiconductor */
100 100

  
101
/* This is the OUI of the gigE PHY in the RealTek 8169S/8110S chips */
102
#define    MII_OUI_xxREALTEK   0x000732    /*  */
101 103

  
102 104
/*
103 105
 * List of known models.  Grouped by oui.
......
178 180
/* RealTek Semiconductor PHYs */
179 181
#define    MII_MODEL_REALTEK_RTL8201L  0x0020
180 182
#define    MII_STR_REALTEK_RTL8201L    "RTL8201L 10/100 media interface"
183
#define    MII_MODEL_xxREALTEK_RTL8169S    0x0011
184
#define    MII_STR_xxREALTEK_RTL8169S  "RTL8169S/8110S media interface"
181 185

  
182 186
/* Seeq PHYs */
183 187
#define    MII_MODEL_xxSEEQ_80220  0x0003
sys/dev/netif/mii_layer/rgephy.c 23 Dec 2005 20:13:42 -0000
1
/*-
2
 * Copyright (c) 2003
3
 *  Bill Paul <wpaul@windriver.com>.  All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 * 1. Redistributions of source code must retain the above copyright
9
 *    notice, this list of conditions and the following disclaimer.
10
 * 2. Redistributions in binary form must reproduce the above copyright
11
 *    notice, this list of conditions and the following disclaimer in the
12
 *    documentation and/or other materials provided with the distribution.
13
 * 3. All advertising materials mentioning features or use of this software
14
 *    must display the following acknowledgement:
15
 *  This product includes software developed by Bill Paul.
16
 * 4. Neither the name of the author nor the names of any co-contributors
17
 *    may be used to endorse or promote products derived from this software
18
 *    without specific prior written permission.
19
 *
20
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30
 * THE POSSIBILITY OF SUCH DAMAGE.
31
 *
32
 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
33
 * $DragonFly: $
34
 */
35

  
36
#include <sys/cdefs.h>
37

  
38
/*
39
 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
40
 */
41

  
42
#include <sys/param.h>
43
#include <sys/systm.h>
44
#include <sys/kernel.h>
45
#include <sys/socket.h>
46
#include <sys/bus.h>
47

  
48
#include <machine/clock.h>
49

  
50
#include <net/if.h>
51
#include <net/if_arp.h>
52
#include <net/if_media.h>
53

  
54
#include <dev/netif/mii_layer/mii.h>
55
#include <dev/netif/mii_layer/miivar.h>
56
#include <dev/netif/mii_layer/rgephyreg.h>
57

  
58
#include "miidevs.h"
59

  
60
#include "miibus_if.h"
61

  
62
#include <machine/bus.h>
63
#include <dev/netif/re/if_rereg.h>
64

  
65
static int  rgephy_probe(device_t);
66
static int  rgephy_attach(device_t);
67
static int  rgephy_detach(device_t);
68
static void rgephy_update(struct mii_softc *, int);
69

  
70
static device_method_t rgephy_methods[] = {
71
    /* device interface */
72
    DEVMETHOD(device_probe,     rgephy_probe),
73
    DEVMETHOD(device_attach,    rgephy_attach),
74
    DEVMETHOD(device_detach,    rgephy_detach),
75
    DEVMETHOD(device_shutdown,  bus_generic_shutdown),
76
    { 0, 0 }
77
};
78

  
79
static devclass_t rgephy_devclass;
80

  
81
static driver_t rgephy_driver = {
82
    "rgephy",
83
    rgephy_methods,
84
    sizeof(struct mii_softc)
85
};
86

  
87
DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
88

  
89
static int  rgephy_service(struct mii_softc *, struct mii_data *, int);
90
static void rgephy_status(struct mii_softc *);
91
static int  rgephy_mii_phy_auto(struct mii_softc *);
92
static void rgephy_reset(struct mii_softc *);
93
static void rgephy_loop(struct mii_softc *);
94
static void rgephy_load_dspcode(struct mii_softc *);
95
static int  rgephy_mii_model;
96

  
97
static int
98
rgephy_probe(device_t dev)
99
{
100
    struct mii_attach_args *ma;
101

  
102
    ma = device_get_ivars(dev);
103

  
104
    if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxREALTEK &&
105
        MII_MODEL(ma->mii_id2) == MII_MODEL_xxREALTEK_RTL8169S) {
106
        device_set_desc(dev, MII_STR_xxREALTEK_RTL8169S);
107
        return(0);
108
    }
109

  
110
    return(ENXIO);
111
}
112

  
113
static int
114
rgephy_attach(device_t dev)
115
{
116
    struct mii_softc *sc;
117
    struct mii_attach_args *ma;
118
    struct mii_data *mii;
119
    const char *sep = "";
120

  
121
    sc = device_get_softc(dev);
122
    ma = device_get_ivars(dev);
123
    sc->mii_dev = device_get_parent(dev);
124
    mii = device_get_softc(sc->mii_dev);
125
    LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
126

  
127
    sc->mii_inst = mii->mii_instance;
128
    sc->mii_phy = ma->mii_phyno;
129
    sc->mii_service = rgephy_service;
130
    sc->mii_pdata = mii;
131

  
132
    sc->mii_flags |= MIIF_NOISOLATE;
133
    mii->mii_instance++;
134

  
135
#define ADD(m, c)   ifmedia_add(&mii->mii_media, (m), (c), NULL)
136
#define PRINT(s)    printf("%s%s", sep, s); sep = ", "
137

  
138
    ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
139
        BMCR_ISO);
140
#if 0
141
    ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
142
        BMCR_LOOP|BMCR_S100);
143
#endif
144

  
145
    rgephy_mii_model = MII_MODEL(ma->mii_id2);
146
    rgephy_reset(sc);
147

  
148
    sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
149
    sc->mii_capabilities &= ~BMSR_ANEG;
150

  
151
    device_printf(dev, " ");
152
    mii_add_media(sc, sc->mii_capabilities);
153
    ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
154
        RGEPHY_BMCR_FDX);
155
    PRINT(", 1000baseTX");
156
    ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
157
    PRINT("1000baseTX-FDX");
158
    ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
159
    PRINT("auto");
160

  
161
    printf("\n");
162
#undef ADD
163
#undef PRINT
164

  
165
    MIIBUS_MEDIAINIT(sc->mii_dev);
166
    return(0);
167
}
168

  
169
static int
170
rgephy_detach(device_t dev)
171
{
172
    struct mii_softc    *sc;
173
    struct mii_data *mii;
174

  
175
    sc = device_get_softc(dev);
176
    mii = device_get_softc(device_get_softc(dev));
177
    mii_phy_auto_stop(sc);
178
    sc->mii_dev = NULL;
179
    LIST_REMOVE(sc, mii_list);
180

  
181
    return (0);
182
}
183

  
184
static void
185
rgephy_update(struct mii_softc *sc, int cmd)
186
{
187
    struct mii_data *mii = sc->mii_pdata;
188

  
189
    if (sc->mii_active != mii->mii_media_active ||
190
        cmd == MII_MEDIACHG) {
191
        MIIBUS_STATCHG(sc->mii_dev);
192
        sc->mii_active = mii->mii_media_active;
193
    }
194
/*
195
    if (sc->mii_status != mii->mii_media_status) {
196
        MIIBUS_LINKCHG(sc->mii_dev);
197
        sc->mii_status = mii->mii_media_status;
198
    }
199
*/
200
}
201

  
202
static int
203
rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
204
{
205
    struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
206
    int reg, speed, gig;
207

  
208
    switch (cmd) {
209
    case MII_POLLSTAT:
210
        /*
211
         * If we're not polling our PHY instance, just return.
212
         */
213
        if (IFM_INST(ife->ifm_media) != sc->mii_inst)
214
            return (0);
215
        break;
216

  
217
    case MII_MEDIACHG:
218
        /*
219
         * If the media indicates a different PHY instance,
220
         * isolate ourselves.
221
         */
222
        if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
223
            reg = PHY_READ(sc, MII_BMCR);
224
            PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
225
            return (0);
226
        }
227

  
228
        /*
229
         * If the interface is not up, don't do anything.
230
         */
231
        if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
232
            break;
233

  
234
        rgephy_reset(sc);   /* XXX hardware bug work-around */
235

  
236
        switch (IFM_SUBTYPE(ife->ifm_media)) {
237
        case IFM_AUTO:
238
#ifdef foo
239
            /*
240
             * If we're already in auto mode, just return.
241
             */
242
            if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
243
                return (0);
244
#endif
245
            (void) rgephy_mii_phy_auto(sc);
246
            break;
247
        case IFM_1000_T:
248
            speed = RGEPHY_S1000;
249
            goto setit;
250
        case IFM_100_TX:
251
            speed = RGEPHY_S100;
252
            goto setit;
253
        case IFM_10_T:
254
            speed = RGEPHY_S10;
255
setit:
256
            rgephy_loop(sc);
257
            if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
258
                speed |= RGEPHY_BMCR_FDX;
259
                gig = RGEPHY_1000CTL_AFD;
260
            } else {
261
                gig = RGEPHY_1000CTL_AHD;
262
            }
263

  
264
            PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
265
            PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
266
            PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
267

  
268
            if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 
269
                break;
270

  
271
            PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
272
            PHY_WRITE(sc, RGEPHY_MII_BMCR,
273
                speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
274

  
275
            /*
276
             * When settning the link manually, one side must
277
             * be the master and the other the slave. However
278
             * ifmedia doesn't give us a good way to specify
279
             * this, so we fake it by using one of the LINK
280
             * flags. If LINK0 is set, we program the PHY to
281
             * be a master, otherwise it's a slave.
282
             */
283
            if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
284
                PHY_WRITE(sc, RGEPHY_MII_1000CTL,
285
                    gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
286
            } else {
287
                PHY_WRITE(sc, RGEPHY_MII_1000CTL,
288
                    gig|RGEPHY_1000CTL_MSE);
289
            }
290
            break;
291
#ifdef foo
292
        case IFM_NONE:
293
            PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
294
            break;
295
#endif
296
        case IFM_100_T4:
297
        default:
298
            return (EINVAL);
299
        }
300
        break;
301

  
302
    case MII_TICK:
303
        /*
304
         * If we're not currently selected, just return.
305
         */
306
        if (IFM_INST(ife->ifm_media) != sc->mii_inst)
307
            return (0);
308

  
309
        /*
310
         * Is the interface even up?
311
         */
312
        if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
313
            return (0);
314

  
315
        /*
316
         * Only used for autonegotiation.
317
         */
318
        if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
319
            break;
320

  
321
        /*
322
         * Check to see if we have link.  If we do, we don't
323
         * need to restart the autonegotiation process.  Read
324
         * the BMSR twice in case it's latched.
325
         */
326
        reg = PHY_READ(sc, RE_GMEDIASTAT);
327
        if (reg & RE_GMEDIASTAT_LINK)
328
            break;
329

  
330
        /*
331
         * Only retry autonegotiation every 17 seconds.
332
         */
333
        if (++sc->mii_ticks <= 17/*10*/)
334
            break;
335
        
336
        sc->mii_ticks = 0;
337
        rgephy_mii_phy_auto(sc);
338
        return (0);
339
    }
340

  
341
    /* Update the media status. */
342
    rgephy_status(sc);
343

  
344
    /*
345
     * Callback if something changed. Note that we need to poke
346
     * the DSP on the RealTek PHYs if the media changes.
347
     *
348
     */
349
    if (sc->mii_active != mii->mii_media_active || 
350
   /* sc->mii_status != mii->mii_media_status || */
351
        cmd == MII_MEDIACHG) {
352
        rgephy_load_dspcode(sc);
353
    }
354
    rgephy_update(sc, cmd);
355
    return (0);
356
}
357

  
358
static void
359
rgephy_status(struct mii_softc *sc)
360
{
361
    struct mii_data *mii = sc->mii_pdata;
362
    int bmsr, bmcr;
363

  
364
    mii->mii_media_status = IFM_AVALID;
365
    mii->mii_media_active = IFM_ETHER;
366

  
367
    bmsr = PHY_READ(sc, RE_GMEDIASTAT);
368

  
369
    if (bmsr & RE_GMEDIASTAT_LINK)
370
        mii->mii_media_status |= IFM_ACTIVE;
371
    bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
372

  
373
    bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
374

  
375
    if (bmcr & RGEPHY_BMCR_LOOP)
376
        mii->mii_media_active |= IFM_LOOP;
377

  
378
    if (bmcr & RGEPHY_BMCR_AUTOEN) {
379
        if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
380
            /* Erg, still trying, I guess... */
381
            mii->mii_media_active |= IFM_NONE;
382
            return;
383
        }
384
    }
385

  
386
    bmsr = PHY_READ(sc, RE_GMEDIASTAT);
387
    if (bmsr & RE_GMEDIASTAT_10MBPS)
388
        mii->mii_media_active |= IFM_10_T;
389
    if (bmsr & RE_GMEDIASTAT_100MBPS)
390
        mii->mii_media_active |= IFM_100_TX;
391
    if (bmsr & RE_GMEDIASTAT_1000MBPS)
392
        mii->mii_media_active |= IFM_1000_T;
393
    if (bmsr & RE_GMEDIASTAT_FDX)
394
        mii->mii_media_active |= IFM_FDX;
395

  
396
    return;
397
}
398

  
399
static int
400
rgephy_mii_phy_auto(struct mii_softc *mii)
401
{
402
    rgephy_loop(mii);
403
    rgephy_reset(mii);
404

  
405
    PHY_WRITE(mii, RGEPHY_MII_ANAR, mii_bmsr_media_to_anar(mii));
406
    DELAY(1000);
407
    PHY_WRITE(mii, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AFD);
408
    DELAY(1000);
409
    PHY_WRITE(mii, RGEPHY_MII_BMCR,
410
        RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
411
    DELAY(100);
412

  
413
    return (EJUSTRETURN);
414
}
415

  
416
static void
417
rgephy_loop(struct mii_softc *sc)
418
{
419
    u_int32_t bmsr;
420
    int i;
421

  
422
    PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
423
    DELAY(1000);
424

  
425
    for (i = 0; i < 15000; i++) {
426
        bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
427
        if (!(bmsr & RGEPHY_BMSR_LINK)) {
428
#if 0
429
            device_printf(sc->mii_dev, "looped %d\n", i);
430
#endif
431
            break;
432
        }
433
        DELAY(10);
434
    }
435
}
436

  
437
#define PHY_SETBIT(x, y, z) \
438
    PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
439
#define PHY_CLRBIT(x, y, z) \
440
    PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
441

  
442
/*
443
 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
444
 * existing revisions of the 8169S/8110S chips need to be tuned in
445
 * order to reliably negotiate a 1000Mbps link. Later revs of the
446
 * chips may not require this software tuning.
447
 */
448
static void
449
rgephy_load_dspcode(struct mii_softc *sc)
450
{
451
    int val;
452

  
453
    PHY_WRITE(sc, 31, 0x0001);
454
    PHY_WRITE(sc, 21, 0x1000);
455
    PHY_WRITE(sc, 24, 0x65C7);
456
    PHY_CLRBIT(sc, 4, 0x0800);
457
    val = PHY_READ(sc, 4) & 0xFFF;
458
    PHY_WRITE(sc, 4, val);
459
    PHY_WRITE(sc, 3, 0x00A1);
460
    PHY_WRITE(sc, 2, 0x0008);
461
    PHY_WRITE(sc, 1, 0x1020);
462
    PHY_WRITE(sc, 0, 0x1000);
463
    PHY_SETBIT(sc, 4, 0x0800);
464
    PHY_CLRBIT(sc, 4, 0x0800);
465
    val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
466
    PHY_WRITE(sc, 4, val);
467
    PHY_WRITE(sc, 3, 0xFF41);
468
    PHY_WRITE(sc, 2, 0xDE60);
469
    PHY_WRITE(sc, 1, 0x0140);
470
    PHY_WRITE(sc, 0, 0x0077);
471
    val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
472
    PHY_WRITE(sc, 4, val);
473
    PHY_WRITE(sc, 3, 0xDF01);
474
    PHY_WRITE(sc, 2, 0xDF20);
475
    PHY_WRITE(sc, 1, 0xFF95);
476
    PHY_WRITE(sc, 0, 0xFA00);
477
    val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
478
    PHY_WRITE(sc, 4, val);
479
    PHY_WRITE(sc, 3, 0xFF41);
480
    PHY_WRITE(sc, 2, 0xDE20);
481
    PHY_WRITE(sc, 1, 0x0140);
482
    PHY_WRITE(sc, 0, 0x00BB);
483
    val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
484
    PHY_WRITE(sc, 4, val);
485
    PHY_WRITE(sc, 3, 0xDF01);
486
    PHY_WRITE(sc, 2, 0xDF20);
487
    PHY_WRITE(sc, 1, 0xFF95);
488
    PHY_WRITE(sc, 0, 0xBF00);
489
    PHY_SETBIT(sc, 4, 0x0800);
490
    PHY_CLRBIT(sc, 4, 0x0800);
491
    PHY_WRITE(sc, 31, 0x0000);
492
    
493
    DELAY(40);
494
}
495

  
496
static void
497
rgephy_reset(struct mii_softc *sc)
498
{
499
    mii_phy_reset(sc);
500
    DELAY(1000);
501
    rgephy_load_dspcode(sc);
502

  
503
    return;
504
}
sys/dev/netif/mii_layer/rgephyreg.h 23 Dec 2005 15:00:20 -0000
1
/*-
2
 * Copyright (c) 2003
3
 * Bill Paul <wpaul@windriver.com>.  All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
7
 * are met:
8
 * 1. Redistributions of source code must retain the above copyright
9
 *    notice, this list of conditions and the following disclaimer.
10
 * 2. Redistributions in binary form must reproduce the above copyright
11
 *    notice, this list of conditions and the following disclaimer in the
12
 *    documentation and/or other materials provided with the distribution.
13
 * 3. All advertising materials mentioning features or use of this software
14
 *    must display the following acknowledgement:
15
 * This product includes software developed by Bill Paul.
16
 * 4. Neither the name of the author nor the names of any co-contributors
17
 *    may be used to endorse or promote products derived from this software
18
 *    without specific prior written permission.
19
 *
20
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30
 * THE POSSIBILITY OF SUCH DAMAGE.
31
 *
32
 * $FreeBSD: src/sys/dev/mii/rgephyreg.h,v 1.2 2005/01/06 01:42:56 imp Exp $
33
 */
34

  
35
#ifndef _DEV_MII_RGEPHYREG_H_
36
#define    _DEV_MII_RGEPHYREG_H_
37

  
38
/*
39
 * RealTek 8169S/8110S gigE PHY registers
40
 */
41

  
42
#define RGEPHY_MII_BMCR        0x00
43
#define RGEPHY_BMCR_RESET  0x8000
44
#define RGEPHY_BMCR_LOOP   0x4000
45
#define RGEPHY_BMCR_SPD0   0x2000  /* speed select, lower bit */
46
#define RGEPHY_BMCR_AUTOEN 0x1000  /* Autoneg enabled */
47
#define RGEPHY_BMCR_PDOWN  0x0800  /* Power down */
48
#define RGEPHY_BMCR_ISO        0x0400  /* Isolate */
49
#define RGEPHY_BMCR_STARTNEG   0x0200  /* Restart autoneg */
50
#define RGEPHY_BMCR_FDX        0x0100  /* Duplex mode */
51
#define RGEPHY_BMCR_CTEST  0x0080  /* Collision test enable */
52
#define RGEPHY_BMCR_SPD1   0x0040  /* Speed select, upper bit */
53

  
54
#define RGEPHY_S1000       RGEPHY_BMCR_SPD1    /* 1000mbps */
55
#define RGEPHY_S100        RGEPHY_BMCR_SPD0    /* 100mpbs */
56
#define RGEPHY_S10     0           /* 10mbps */
57

  
58
#define RGEPHY_MII_BMSR        0x01
59
#define RGEPHY_BMSR_100T4  0x8000  /* 100 base T4 capable */
60
#define RGEPHY_BMSR_100TXFDX   0x4000  /* 100 base Tx full duplex capable */
61
#define RGEPHY_BMSR_100TXHDX   0x2000  /* 100 base Tx half duplex capable */
62
#define RGEPHY_BMSR_10TFDX 0x1000  /* 10 base T full duplex capable */
63
#define RGEPHY_BMSR_10THDX 0x0800  /* 10 base T half duplex capable */
64
#define RGEPHY_BMSR_100T2FDX   0x0400  /* 100 base T2 full duplex capable */
65
#define RGEPHY_BMSR_100T2HDX   0x0200  /* 100 base T2 half duplex capable */
66
#define RGEPHY_BMSR_EXTSTS 0x0100  /* Extended status present */
67
#define RGEPHY_BMSR_PRESUB 0x0040  /* Preamble surpression */
68
#define RGEPHY_BMSR_ACOMP  0x0020  /* Autoneg complete */
69
#define RGEPHY_BMSR_RFAULT 0x0010  /* Remote fault condition occured */
70
#define RGEPHY_BMSR_ANEG   0x0008  /* Autoneg capable */
71
#define RGEPHY_BMSR_LINK   0x0004  /* Link status */
72
#define RGEPHY_BMSR_JABBER 0x0002  /* Jabber detected */
73
#define RGEPHY_BMSR_EXT        0x0001  /* Extended capability */
74

  
75
#define RGEPHY_MII_ANAR        0x04
76
#define RGEPHY_ANAR_NP     0x8000  /* Next page */
77
#define RGEPHY_ANAR_RF     0x2000  /* Remote fault */
78
#define RGEPHY_ANAR_ASP        0x0800  /* Asymmetric Pause */
79
#define RGEPHY_ANAR_PC     0x0400  /* Pause capable */
80
#define RGEPHY_ANAR_T4     0x0200  /* local device supports 100bT4 */
81
#define RGEPHY_ANAR_TX_FD  0x0100  /* local device supports 100bTx FD */
82
#define RGEPHY_ANAR_TX     0x0080  /* local device supports 100bTx */
83
#define RGEPHY_ANAR_10_FD  0x0040  /* local device supports 10bT FD */
84
#define RGEPHY_ANAR_10     0x0020  /* local device supports 10bT */
85
#define RGEPHY_ANAR_SEL        0x001F  /* selector field, 00001=Ethernet */
86

  
87
#define RGEPHY_MII_ANLPAR  0x05
88
#define RGEPHY_ANLPAR_NP   0x8000  /* Next page */
89
#define RGEPHY_ANLPAR_RF   0x2000  /* Remote fault */
90
#define RGEPHY_ANLPAR_ASP  0x0800  /* Asymmetric Pause */
91
#define RGEPHY_ANLPAR_PC   0x0400  /* Pause capable */
92
#define RGEPHY_ANLPAR_T4   0x0200  /* link partner supports 100bT4 */
93
#define RGEPHY_ANLPAR_TX_FD    0x0100  /* link partner supports 100bTx FD */
94
#define RGEPHY_ANLPAR_TX   0x0080  /* link partner supports 100bTx */
95
#define RGEPHY_ANLPAR_10_FD    0x0040  /* link partner supports 10bT FD */
96
#define RGEPHY_ANLPAR_10   0x0020  /* link partner supports 10bT */
97
#define RGEPHY_ANLPAR_SEL  0x001F  /* selector field, 00001=Ethernet */
98

  
99
#define RGEPHY_SEL_TYPE        0x0001  /* ethernet */
100

  
101
#define RGEPHY_MII_ANER        0x06
102
#define RGEPHY_ANER_PDF        0x0010  /* Parallel detection fault */
103
#define RGEPHY_ANER_LPNP   0x0008  /* Link partner can next page */
104
#define RGEPHY_ANER_NP     0x0004  /* Local PHY can next page */
105
#define RGEPHY_ANER_RX     0x0002  /* Next page received */
106
#define RGEPHY_ANER_LPAN   0x0001  /* Link partner autoneg capable */
107

  
108
#define RGEPHY_MII_NEXTP   0x07    /* Next page */
109

  
110
#define RGEPHY_MII_NEXTP_LP    0x08    /* Next page of link partner */
111

  
112
#define RGEPHY_MII_1000CTL 0x09    /* 1000baseT control */
113
#define RGEPHY_1000CTL_TST 0xE000  /* test modes */
114
#define RGEPHY_1000CTL_MSE 0x1000  /* Master/Slave manual enable */
115
#define RGEPHY_1000CTL_MSC 0x0800  /* Master/Slave select */
116
#define RGEPHY_1000CTL_RD  0x0400  /* Repeater/DTE */
117
#define RGEPHY_1000CTL_AFD 0x0200  /* Advertise full duplex */
118
#define RGEPHY_1000CTL_AHD 0x0100  /* Advertise half duplex */
119

  
120
#define RGEPHY_TEST_TX_JITTER          0x2000
121
#define RGEPHY_TEST_TX_JITTER_MASTER_MODE  0x4000
122
#define RGEPHY_TEST_TX_JITTER_SLAVE_MODE   0x6000
123
#define RGEPHY_TEST_TX_DISTORTION      0x8000
124

  
125
#define RGEPHY_MII_1000STS 0x0A    /* 1000baseT status */
126
#define RGEPHY_1000STS_MSF 0x8000  /* Master/slave fault */
127
#define RGEPHY_1000STS_MSR 0x4000  /* Master/slave result */
128
#define RGEPHY_1000STS_LRS 0x2000  /* Local receiver status */
129
#define RGEPHY_1000STS_RRS 0x1000  /* Remote receiver status */
130
#define RGEPHY_1000STS_LPFD    0x0800  /* Link partner can FD */
131
#define RGEPHY_1000STS_LPHD    0x0400  /* Link partner can HD */
132
#define RGEPHY_1000STS_IEC 0x00FF  /* Idle error count */
133

  
134
#define RGEPHY_MII_EXTSTS  0x0F    /* Extended status */
135
#define RGEPHY_EXTSTS_X_FD_CAP 0x8000  /* 1000base-X FD capable */
136
#define RGEPHY_EXTSTS_X_HD_CAP 0x4000  /* 1000base-X HD capable */
137
#define RGEPHY_EXTSTS_T_FD_CAP 0x2000  /* 1000base-T FD capable */
138
#define RGEPHY_EXTSTS_T_HD_CAP 0x1000  /* 1000base-T HD capable */
139

  
140

  
141

  
142
#endif /* _DEV_RGEPHY_MIIREG_H_ */