Bug #2814 ยป pstate.patch
| sys/platform/pc64/acpica/acpi_pstate_machdep.c | ||
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#define AMD_APMI_HWPSTATE 0x80
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#define AMD_MSR_PSTATE_CSR_MASK 0x7ULL
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#define AMD1X_MSR_PSTATE_LIMIT 0xc0010061
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#define AMD1X_MSR_PSTATE_CTL 0xc0010062
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#define AMD1X_MSR_PSTATE_ST 0xc0010063
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#define AMD_MSR_PSTATE_EN 0x8000000000000000ULL
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#define AMD10_MSR_PSTATE_START 0xc0010064
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#define AMD10_MSR_PSTATE_COUNT 5
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#define AMD0F_PST_CTL_FID(cval) (((cval) >> 0) & 0x3f)
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#define AMD0F_PST_CTL_VID(cval) (((cval) >> 6) & 0x1f)
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| ... | ... | |
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static int
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acpi_pst_amd10_check_pstates(const struct acpi_pstate *pstates, int npstates)
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{
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/* Only P0-P4 are supported */
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if (npstates > AMD10_MSR_PSTATE_COUNT) {
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kprintf("cpu%d: only P0-P4 is allowed\n", mycpuid);
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return EINVAL;
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}
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uint64_t count;
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count = rdmsr(AMD1X_MSR_PSTATE_LIMIT);
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count = 1 + ((count >> 4) & 0x7);
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return acpi_pst_amd1x_check_pstates(pstates, npstates,
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AMD10_MSR_PSTATE_START,
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AMD10_MSR_PSTATE_START + AMD10_MSR_PSTATE_COUNT);
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AMD10_MSR_PSTATE_START + (uint32_t)count);
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}
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static int
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