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Submit #3265 » 1-add.diff

chicken, 01/30/2021 02:12 AM

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sys/cpu/x86_64/include/specialreg.h
35 35
#define	_CPU_SPECIALREG_H_
36 36

  
37 37
/*
38
 * Bits in 386 special registers:
38
 * Bits in CR0 special register
39 39
 */
40 40
#define	CR0_PE	0x00000001	/* Protected mode Enable */
41 41
#define	CR0_MP	0x00000002	/* "Math" (fpu) Present */
42 42
#define	CR0_EM	0x00000004	/* EMulate FPU instructions. (trap ESC only) */
43 43
#define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
44
#define	CR0_PG	0x80000000	/* Paging enable */
45

  
46
/*
47
 * Bits in 486 special registers:
48
 */
44
#define	CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
49 45
#define	CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
50 46
#define	CR0_WP	0x00010000	/* Write Protect (honor page protect in	all modes) */
51 47
#define	CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
52
#define	CR0_NW  0x20000000	/* Not Write-through */
53
#define	CR0_CD  0x40000000	/* Cache Disable */
48
#define	CR0_NW	0x20000000	/* Not Write-through */
49
#define	CR0_CD	0x40000000	/* Cache Disable */
50
#define	CR0_PG	0x80000000	/* Paging enable */
54 51

  
55 52
/*
56 53
 * Bits in CR4 special register
......
66 63
#define	CR4_PCE		0x00000100	/* Performance monitoring counter enable */
67 64
#define	CR4_FXSR	0x00000200	/* Fast FPU save/restore used by OS */
68 65
#define	CR4_XMM		0x00000400	/* Enable SIMD/MMX2 to use except 16 */
66
#define	CR4_UMIP	0x00000800	/* User-mode instruction prevention */
67
#define	CR4_LA57	0x00001000	/* 57-bit linear addresses */
69 68
#define	CR4_VMXE	0x00002000	/* Enables VMX - Intel specific */
69
#define	CR4_SMXE	0x00004000	/* Enable SMX - Intel specific */
70
#define	CR4_FSGSBASE	0x00010000	/* Enable *FSBASE and *GSBASE insns */
71
#define	CR4_PCIDE	0x00020000	/* Enable Process Context IDentifiers */
70 72
#define	CR4_XSAVE	0x00040000	/* Enable XSave (for AVX Instructions)*/
71 73
#define	CR4_SMEP	0x00100000	/* Supervisor-Mode Execution Prevent */
72 74
#define	CR4_SMAP	0x00200000	/* Supervisor-Mode Access Prevent */
73
#define	CR4_PKE		0x00400000	/* Protection Keys Enable */
74

  
75
#define	CR4_PKE		0x00400000	/* Protection Keys Enable for user pages */
76
#define	CR4_CET		0x00800000	/* Enable CET */
77
#define	CR4_PKS		0x01000000	/* Protection Keys Enable for kern pages */
75 78

  
76 79
/*
77 80
 * Bits in x86_64 special registers.  EFER is 64 bits wide.
78 81
 */
79
#define	EFER_SCE	0x000000001	/* System Call Extensions (R/W) */
80
#define	EFER_LME	0x000000100	/* Long mode enable (R/W) */
81
#define	EFER_LMA	0x000000400	/* Long mode active (R) */
82
#define	EFER_NXE	0x000000800	/* PTE No-Execute bit enable (R/W) */
83
#define	EFER_SVME	0x000001000	/* SVM Enable (R/W) */
82
#define	EFER_SCE	0x00000001	/* System Call Extensions (R/W) */
83
#define	EFER_LME	0x00000100	/* Long mode enable (R/W) */
84
#define	EFER_LMA	0x00000400	/* Long mode active (R) */
85
#define	EFER_NXE	0x00000800	/* PTE No-Execute bit enable (R/W) */
86
#define	EFER_SVME	0x00001000	/* SVM Enable (R/W) */
87
#define	EFER_LMSLE	0x00002000	/* Long Mode Segment Limit Enable */
88
#define	EFER_FFXSR	0x00004000	/* Fast FXSAVE/FXRSTOR Enable */
89
#define	EFER_TCE	0x00008000	/* Translation Cache Ext. */
90
#define	EFER_MCOMMIT	0x00020000	/* MCOMMIT Enable */
91
#define	EFER_INTWB	0x00040000	/* Intr WBINVD/WBNOINVD Enable */
84 92

  
85 93
/*
86 94
 * CPUID instruction features register
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