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Submit #3265 » 2-rename.diff

chicken, 01/30/2021 02:12 AM

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sys/cpu/x86_64/include/specialreg.h
61 61
#define	CR4_MCE		0x00000040	/* Machine check enable */
62 62
#define	CR4_PGE		0x00000080	/* Page global enable */
63 63
#define	CR4_PCE		0x00000100	/* Performance monitoring counter enable */
64
#define	CR4_FXSR	0x00000200	/* Fast FPU save/restore used by OS */
65
#define	CR4_XMM		0x00000400	/* Enable SIMD/MMX2 to use except 16 */
64
#define	CR4_OSFXSR	0x00000200	/* Fast FPU save/restore used by OS */
65
#define	CR4_OSXMMEXCPT	0x00000400	/* Enable SIMD/MMX2 to use except 16 */
66 66
#define	CR4_UMIP	0x00000800	/* User-mode instruction prevention */
67 67
#define	CR4_LA57	0x00001000	/* 57-bit linear addresses */
68 68
#define	CR4_VMXE	0x00002000	/* Enables VMX - Intel specific */
69 69
#define	CR4_SMXE	0x00004000	/* Enable SMX - Intel specific */
70 70
#define	CR4_FSGSBASE	0x00010000	/* Enable *FSBASE and *GSBASE insns */
71 71
#define	CR4_PCIDE	0x00020000	/* Enable Process Context IDentifiers */
72
#define	CR4_XSAVE	0x00040000	/* Enable XSave (for AVX Instructions)*/
72
#define	CR4_OSXSAVE	0x00040000	/* Enable XSave (for AVX Instructions)*/
73 73
#define	CR4_SMEP	0x00100000	/* Supervisor-Mode Execution Prevent */
74 74
#define	CR4_SMAP	0x00200000	/* Supervisor-Mode Access Prevent */
75 75
#define	CR4_PKE		0x00400000	/* Protection Keys Enable for user pages */
......
465 465
#define IA32_ARCH_CAP_IBRS_ALL	0x00000002
466 466
#define IA32_ARCH_CAP_RSBA	0x00000004
467 467
#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY	0x00000008
468
#define IA32_ARCH_SSB_NO	0x00000010
469
#define IA32_ARCH_MDS_NO	0x00000020
468
#define IA32_ARCH_CAP_SSB_NO	0x00000010
469
#define IA32_ARCH_CAP_MDS_NO	0x00000020
470 470
#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO		0x00000040
471 471
#define IA32_ARCH_CAP_TSX_CTRL	0x00000080
472 472
#define IA32_ARCH_CAP_TAA_NO	0x00000100
sys/platform/pc64/vmm/vmx.c
898 898
	/* Set the CR0/CR4 registers, removing the unsupported bits */
899 899
	vti->guest_cr0 = (CR0_PE | CR0_PG | cr0_fixed_to_1) & ~cr0_fixed_to_0;
900 900
	ERROR_IF(vmwrite(VMCS_GUEST_CR0, vti->guest_cr0));
901
	ERROR_IF(vmwrite(VMCS_GUEST_CR4, (CR4_PAE | CR4_FXSR | CR4_XMM | CR4_XSAVE |
902
	    cr4_fixed_to_1) & ~cr4_fixed_to_0));
901
	ERROR_IF(vmwrite(VMCS_GUEST_CR4, (CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT
902
	    | CR4_OSXSAVE | cr4_fixed_to_1) & ~cr4_fixed_to_0));
903 903

  
904 904
	/* Don't set EFER_SCE for catching "syscall" instructions */
905 905
	ERROR_IF(vmwrite(VMCS_GUEST_IA32_EFER, (EFER_LME | EFER_LMA)));
sys/platform/pc64/x86_64/initcpu.c
212 212
	 * Check for FXSR and SSE support and enable if available
213 213
	 */
214 214
	if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
215
		load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
215
		load_cr4(rcr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
216 216
		cpu_fxsr = hw_instruction_sse = 1;
217 217
	}
218 218

  
......
224 224
#if !defined(CPU_DISABLE_AVX)
225 225
	/* Use XSAVE if supported */
226 226
	if (cpu_feature2 & CPUID2_XSAVE) {
227
		load_cr4(rcr4() | CR4_XSAVE);
227
		load_cr4(rcr4() | CR4_OSXSAVE);
228 228

  
229 229
		/* Adjust size of savefpu in npx.h before adding to mask.*/
230 230
		npx_xcr0_mask = CPU_XFEATURE_X87 | CPU_XFEATURE_SSE;
sys/platform/pc64/x86_64/npx.c
124 124

  
125 125
	crit_enter();
126 126
	stop_emulating();
127
	load_cr4(rcr4() | CR4_FXSR);
127
	load_cr4(rcr4() | CR4_OSFXSR);
128 128
	fxsave(&dummy);
129 129
	npx_mxcsr_mask = ((uint32_t *)&dummy)[7];
130 130
	start_emulating();
sys/platform/pc64/x86_64/vm_machdep.c
904 904
		cpuid_count(7, 0, p);
905 905
		if (p[3] & CPUID_SEF_ARCH_CAP) {
906 906
			msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
907
			if (msr & IA32_ARCH_MDS_NO)
907
			if (msr & IA32_ARCH_CAP_MDS_NO)
908 908
				rv = MDS_NOT_REQUIRED;
909 909
		}
910 910
		if (p[3] & CPUID_SEF_AVX512_4VNNIW)
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