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Submit #3265 » 2-rename.diff

Anonymous, 01/30/2021 02:12 AM

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sys/cpu/x86_64/include/specialreg.h
#define CR4_MCE 0x00000040 /* Machine check enable */
#define CR4_PGE 0x00000080 /* Page global enable */
#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_XMM 0x00000400 /* Enable SIMD/MMX2 to use except 16 */
#define CR4_OSFXSR 0x00000200 /* Fast FPU save/restore used by OS */
#define CR4_OSXMMEXCPT 0x00000400 /* Enable SIMD/MMX2 to use except 16 */
#define CR4_UMIP 0x00000800 /* User-mode instruction prevention */
#define CR4_LA57 0x00001000 /* 57-bit linear addresses */
#define CR4_VMXE 0x00002000 /* Enables VMX - Intel specific */
#define CR4_SMXE 0x00004000 /* Enable SMX - Intel specific */
#define CR4_FSGSBASE 0x00010000 /* Enable *FSBASE and *GSBASE insns */
#define CR4_PCIDE 0x00020000 /* Enable Process Context IDentifiers */
#define CR4_XSAVE 0x00040000 /* Enable XSave (for AVX Instructions)*/
#define CR4_OSXSAVE 0x00040000 /* Enable XSave (for AVX Instructions)*/
#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevent */
#define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevent */
#define CR4_PKE 0x00400000 /* Protection Keys Enable for user pages */
......
#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
#define IA32_ARCH_CAP_RSBA 0x00000004
#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
#define IA32_ARCH_SSB_NO 0x00000010
#define IA32_ARCH_MDS_NO 0x00000020
#define IA32_ARCH_CAP_SSB_NO 0x00000010
#define IA32_ARCH_CAP_MDS_NO 0x00000020
#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
#define IA32_ARCH_CAP_TSX_CTRL 0x00000080
#define IA32_ARCH_CAP_TAA_NO 0x00000100
sys/platform/pc64/vmm/vmx.c
/* Set the CR0/CR4 registers, removing the unsupported bits */
vti->guest_cr0 = (CR0_PE | CR0_PG | cr0_fixed_to_1) & ~cr0_fixed_to_0;
ERROR_IF(vmwrite(VMCS_GUEST_CR0, vti->guest_cr0));
ERROR_IF(vmwrite(VMCS_GUEST_CR4, (CR4_PAE | CR4_FXSR | CR4_XMM | CR4_XSAVE |
cr4_fixed_to_1) & ~cr4_fixed_to_0));
ERROR_IF(vmwrite(VMCS_GUEST_CR4, (CR4_PAE | CR4_OSFXSR | CR4_OSXMMEXCPT
| CR4_OSXSAVE | cr4_fixed_to_1) & ~cr4_fixed_to_0));
/* Don't set EFER_SCE for catching "syscall" instructions */
ERROR_IF(vmwrite(VMCS_GUEST_IA32_EFER, (EFER_LME | EFER_LMA)));
sys/platform/pc64/x86_64/initcpu.c
* Check for FXSR and SSE support and enable if available
*/
if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
load_cr4(rcr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
cpu_fxsr = hw_instruction_sse = 1;
}
......
#if !defined(CPU_DISABLE_AVX)
/* Use XSAVE if supported */
if (cpu_feature2 & CPUID2_XSAVE) {
load_cr4(rcr4() | CR4_XSAVE);
load_cr4(rcr4() | CR4_OSXSAVE);
/* Adjust size of savefpu in npx.h before adding to mask.*/
npx_xcr0_mask = CPU_XFEATURE_X87 | CPU_XFEATURE_SSE;
sys/platform/pc64/x86_64/npx.c
crit_enter();
stop_emulating();
load_cr4(rcr4() | CR4_FXSR);
load_cr4(rcr4() | CR4_OSFXSR);
fxsave(&dummy);
npx_mxcsr_mask = ((uint32_t *)&dummy)[7];
start_emulating();
sys/platform/pc64/x86_64/vm_machdep.c
cpuid_count(7, 0, p);
if (p[3] & CPUID_SEF_ARCH_CAP) {
msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
if (msr & IA32_ARCH_MDS_NO)
if (msr & IA32_ARCH_CAP_MDS_NO)
rv = MDS_NOT_REQUIRED;
}
if (p[3] & CPUID_SEF_AVX512_4VNNIW)
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