Bug #271 ยป acpi_cpu.c.diff
| acpi_cpu.c 1 Aug 2006 13:19:59 -0000 | ||
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#define ACPI_CPU_NOTIFY_PERF_STATES 0x80 /* _PSS changed. */
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#define ACPI_CPU_NOTIFY_CX_STATES 0x81 /* _CST changed. */
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#define CPU_QUIRK_NO_C3 0x0001 /* C3-type states are not usable. */
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#define CPU_QUIRK_NO_THROTTLE 0x0002 /* Throttling is not usable. */
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#define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
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#define CPU_QUIRK_NO_THROTTLE (1<<1) /* Throttling is not usable. */
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#define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
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#define PCI_VENDOR_INTEL 0x8086
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#define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
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ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
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/* Bus mastering arbitration control is needed for C3. */
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/*
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* Bus mastering arbitration control is needed to keep caches coherent
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* while sleeping in C3. If it's not present but a working flush cache
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* instruction is present, flush the caches before entering C3 instead.
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* Otherwise, just disable C3 completely.
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*/
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if (AcpiGbl_FADT->V1_Pm2CntBlk == 0 || AcpiGbl_FADT->Pm2CntLen == 0) {
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cpu_quirks |= CPU_QUIRK_NO_C3;
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"acpi_cpu%d: No BM control, C3 disabled\n",
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device_get_unit(sc->cpu_dev)));
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if (AcpiGbl_FADT->WbInvd && AcpiGbl_FADT->WbInvdFlush == 0) {
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cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"acpi_cpu%d: no BM control, using flush cache method\n",
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device_get_unit(sc->cpu_dev)));
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} else {
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cpu_quirks |= CPU_QUIRK_NO_C3;
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"acpi_cpu%d: no BM control, C3 not available\n",
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device_get_unit(sc->cpu_dev)));
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}
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}
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/*
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* driver polling for new devices keeps this bit set all the
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* time if USB is loaded.
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*/
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AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active,
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ACPI_MTX_DO_NOT_LOCK);
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if (bm_active != 0) {
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AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1,
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ACPI_MTX_DO_NOT_LOCK);
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cx_next_idx = min(cx_next_idx, cpu_non_c3);
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if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
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AcpiGetRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active,
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ACPI_MTX_DO_NOT_LOCK);
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if (bm_active != 0) {
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AcpiSetRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1,
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ACPI_MTX_DO_NOT_LOCK);
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cx_next_idx = min(cx_next_idx, cpu_non_c3);
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}
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}
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/* Select the next state and update statistics. */
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return;
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}
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/* For C3, disable bus master arbitration and enable bus master wake. */
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/*
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* For C3, disable bus master arbitration and enable bus master wake
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* if BM control is available, otherwise flush the CPU cache.
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*/
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if (cx_next->type == ACPI_STATE_C3) {
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AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK);
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AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1, ACPI_MTX_DO_NOT_LOCK);
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if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
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AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK);
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AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 1,
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ACPI_MTX_DO_NOT_LOCK);
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} else
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ACPI_FLUSH_CPU_CACHE();
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}
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/*
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AcpiHwLowLevelRead(32, &end_time, &AcpiGbl_FADT->XPmTmrBlk);
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/* Enable bus master arbitration and disable bus master wakeup. */
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if (cx_next->type == ACPI_STATE_C3) {
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if (cx_next->type == ACPI_STATE_C3 &&
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(cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
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AcpiSetRegister(ACPI_BITREG_ARB_DISABLE, 0, ACPI_MTX_DO_NOT_LOCK);
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AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0, ACPI_MTX_DO_NOT_LOCK);
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}
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{
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/*
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* C3 is not supported on multiple CPUs since this would require
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* flushing all caches which is currently too expensive.
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* C3 on multiple CPUs requires using the expensive flush cache
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* instruction.
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*/
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if (ncpus > 1)
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cpu_quirks |= CPU_QUIRK_NO_C3;
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cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
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#ifdef notyet
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/* Look for various quirks of the PIIX4 part. */
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