DragonFlyBSD

maxv suggested:

- For the TSC stuff, I think you're right. I had made a half-hearted attempt at keeping a TSC ~mostly
    regular, but this introduces shifts between VCPUs, and it's shitty. The best way to fix it is probably
    to take the TSC field out of the MSR group, and move it into its own NVMM_X64_STATE_TSC group. Then in
    Qemu the impl should be changed, and probably be like WHPX's:
        https://github.com/qemu/qemu/blob/master/target/i386/whpx/whpx-all.c#L463
    Ie the TSC is set only during resets, to zero.