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Bug #835 ยป i386-support-removal.patch

hasso, 11/07/2007 11:46 AM

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share/doc/handbook/handbook.txt
This is the machine architecture. It must be either i386, or amd64.
cpu I386_CPU
cpu I486_CPU
cpu I586_CPU
cpu I686_CPU
share/man/man7/tuning.7
options that can be commented out.
If you only want the kernel to run
on a Pentium class CPU, you can easily remove
.Dv I386_CPU
and
.Dv I486_CPU ,
but only remove
.Dv I586_CPU
if you are sure your CPU is being recognized as a Pentium II or better.
Some clones may be recognized as a Pentium or even a 486 and not be able
to boot without those options.
Some clones may be recognized as a Pentium and not be able to boot
without those options.
If it works, great!
The operating system
will be able to better-use higher-end CPU features for MMU, task switching,
sys/config/GENERIC
platform pc32
machine i386
machine_arch i386
cpu I386_CPU
cpu I486_CPU
cpu I586_CPU
cpu I686_CPU
sys/config/LINT
#
# An SMP kernel will ONLY run on an Intel MP spec. qualified motherboard.
#
# Be sure to disable 'cpu I386_CPU' && 'cpu I486_CPU' for SMP kernels.
# Be sure to disable 'cpu I486_CPU' for SMP kernels.
#
# Check the 'Rogue SMP hardware' section to see if additional options
# are required by your hardware.
......
#
# You must specify at least one CPU (the one you intend to run on);
# deleting the specification for CPUs you don't need to use may make
# parts of the system run faster. This is especially true removing
# I386_CPU.
# parts of the system run faster.
#
cpu I386_CPU
cpu I486_CPU
cpu I586_CPU # aka Pentium(tm)
cpu I686_CPU # aka Pentium Pro(tm)
sys/cpu/i386/include/atomic.h
* if (*_dst == _old) *_dst = _new (all 32 bit words)
*
* Returns 0 on failure, non-zero on success
*
* WARNING:
* This is a !I386_CPU function. For I386_CPU, a _slower and horrible_
* version may be used by the dynamic linker
*/
#if defined(KLD_MODULE)
extern int atomic_cmpset_int(volatile u_int *_dst, u_int _old, u_int _new);
sys/cpu/i386/include/endian.h
#if defined(__GNUC__) || defined(__INTEL_COMPILER_with_DragonFly_endian)
#if (defined(_KERNEL) && !defined(I386_CPU) && \
(defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))) || \
defined(__i486__) || defined(__i586__) || defined(__i686__) || \
defined(__k6__) || defined(__athlon__) || defined(__k8__) || \
defined(__pentium4__)
#define __byte_swap32_var(x) \
__extension__ ({ register __uint32_t __X = (x); \
__asm ("bswap %0" : "+r" (__X)); \
__X; })
#else /* !I386_CPU */
#define __byte_swap32_var(x) \
__extension__ ({ register __uint32_t __X = (x); \
__asm ("xchgb %h0, %b0\n\trorl $16, %0\n\txchgb %h0, %b0" \
: "+q" (__X)); \
__X; })
#endif /* !I386_CPU */
#define __byte_swap16_var(x) \
__extension__ ({ register __uint16_t __X = (x); \
sys/crypto/blowfish/arch/i386/bf_enc.S
* XXX Should use CPP symbols defined as a result of
* XXX `cc -mcpu=pentiumpro'.
*/
#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
#if defined(I486_CPU) || defined(I586_CPU)
#include "bf_enc_586.S"
#else
#include "bf_enc_686.S"
sys/platform/pc32/conf/options
CPU_ATHLON_SSE_HACK opt_cpu.h
# The CPU type affects the endian conversion functions all over the kernel.
I386_CPU opt_global.h
I486_CPU opt_global.h
I586_CPU opt_global.h
I686_CPU opt_global.h
sys/platform/pc32/i386/identcpu.c
case CPUCLASS_286:
kprintf("286");
break;
#if defined(I386_CPU)
case CPUCLASS_386:
kprintf("386");
break;
#endif
#if defined(I486_CPU)
case CPUCLASS_486:
kprintf("486");
......
panicifcpuunsupported(void)
{
#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
#error This kernel is not configured for one of the supported CPUs
#endif
/*
......
* let them know if that machine type isn't configured.
*/
switch (cpu_class) {
case CPUCLASS_286: /* a 286 should not make it this far, anyway */
#if !defined(I386_CPU)
/*
* A 286 and 386 should not make it this far, anyway.
*/
case CPUCLASS_286:
case CPUCLASS_386:
#endif
#if !defined(I486_CPU)
case CPUCLASS_486:
#endif
sys/platform/pc32/i386/machdep.c
cr0 = rcr0();
cr0 |= CR0_NE; /* Done by npxinit() */
cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
#ifdef I386_CPU
if (cpu_class != CPUCLASS_386)
#endif
cr0 |= CR0_WP | CR0_AM;
cr0 |= CR0_WP | CR0_AM;
load_cr0(cr0);
load_gs(_udatasel);
}
sys/platform/pc32/i386/support.s
*/
/*
* copyout(from_kernel, to_user, len) - MP SAFE (if not I386_CPU)
* copyout(from_kernel, to_user, len) - MP SAFE
*/
ENTRY(copyout)
movl PCPU(curthread),%eax
......
cmpl $VM_MAX_USER_ADDRESS,%eax
ja copyout_fault1
#if defined(I386_CPU)
#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
cmpl $CPUCLASS_386,cpu_class
jne 3f
#endif
/*
* We have to check each PTE for user write permission.
* The checking may cause a page fault, so it is important to set
* up everything for return via copyout_fault before here.
*/
/* compute number of pages */
movl %edi,%ecx
andl $PAGE_MASK,%ecx
addl %ebx,%ecx
decl %ecx
shrl $IDXSHIFT+2,%ecx
incl %ecx
/* compute PTE offset for start address */
movl %edi,%edx
shrl $IDXSHIFT,%edx
andb $0xfc,%dl
1:
/* check PTE for each page */
leal PTmap(%edx),%eax
shrl $IDXSHIFT,%eax
andb $0xfc,%al
testb $PG_V,PTmap(%eax) /* PTE page must be valid */
je 4f
movb PTmap(%edx),%al
andb $PG_V|PG_RW|PG_U,%al /* page must be valid and user writable */
cmpb $PG_V|PG_RW|PG_U,%al
je 2f
4:
/* simulate a trap */
pushl %edx
pushl %ecx
shll $IDXSHIFT,%edx
pushl %edx
call trapwrite /* trapwrite(addr) */
popl %edx
popl %ecx
popl %edx
testl %eax,%eax /* if not ok, return EFAULT */
jnz copyout_fault1
2:
addl $4,%edx
decl %ecx
jnz 1b /* check next page */
#endif /* I386_CPU */
/*
* Convert copyout to memcpy_vector(dest:%edi, src:%esi, conut:%ecx)
*/
3:
movl %ebx,%ecx
call *memcpy_vector
......
ret
/*
* su{byte,sword,word} - MP SAFE (if not I386_CPU)
* su{byte,sword,word} - MP SAFE
*
* Write a byte (word, longword) to user memory
*/
......
movl $fusufault,PCB_ONFAULT(%ecx)
movl 4(%esp),%edx
#if defined(I386_CPU)
#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
cmpl $CPUCLASS_386,cpu_class
jne 2f /* we only have to set the right segment selector */
#endif /* I486_CPU || I586_CPU || I686_CPU */
/* XXX - page boundary crossing is still not handled */
movl %edx,%eax
shrl $IDXSHIFT,%edx
andb $0xfc,%dl
leal PTmap(%edx),%ecx
shrl $IDXSHIFT,%ecx
andb $0xfc,%cl
testb $PG_V,PTmap(%ecx) /* PTE page must be valid */
je 4f
movb PTmap(%edx),%dl
andb $PG_V|PG_RW|PG_U,%dl /* page must be valid and user writable */
cmpb $PG_V|PG_RW|PG_U,%dl
je 1f
4:
/* simulate a trap */
pushl %eax
call trapwrite
popl %edx /* remove junk parameter from stack */
testl %eax,%eax
jnz fusufault
1:
movl 4(%esp),%edx
#endif
2:
cmpl $VM_MAX_USER_ADDRESS-4,%edx /* verify address validity */
ja fusufault
......
ret
/*
* susword - MP SAFE (if not I386_CPU)
* susword - MP SAFE
*/
ENTRY(susword)
movl PCPU(curthread),%ecx
......
movl $fusufault,PCB_ONFAULT(%ecx)
movl 4(%esp),%edx
#if defined(I386_CPU)
#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
cmpl $CPUCLASS_386,cpu_class
jne 2f
#endif /* I486_CPU || I586_CPU || I686_CPU */
/* XXX - page boundary crossing is still not handled */
movl %edx,%eax
shrl $IDXSHIFT,%edx
andb $0xfc,%dl
leal PTmap(%edx),%ecx
shrl $IDXSHIFT,%ecx
andb $0xfc,%cl
testb $PG_V,PTmap(%ecx) /* PTE page must be valid */
je 4f
movb PTmap(%edx),%dl
andb $PG_V|PG_RW|PG_U,%dl /* page must be valid and user writable */
cmpb $PG_V|PG_RW|PG_U,%dl
je 1f
4:
/* simulate a trap */
pushl %eax
call trapwrite
popl %edx /* remove junk parameter from stack */
testl %eax,%eax
jnz fusufault
1:
movl 4(%esp),%edx
#endif
2:
cmpl $VM_MAX_USER_ADDRESS-2,%edx /* verify address validity */
ja fusufault
......
ret
/*
* subyte - MP SAFE (if not I386_CPU)
* subyte - MP SAFE
*/
ENTRY(subyte)
movl PCPU(curthread),%ecx
......
movl $fusufault,PCB_ONFAULT(%ecx)
movl 4(%esp),%edx
#if defined(I386_CPU)
#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
cmpl $CPUCLASS_386,cpu_class
jne 2f
#endif /* I486_CPU || I586_CPU || I686_CPU */
movl %edx,%eax
shrl $IDXSHIFT,%edx
andb $0xfc,%dl
leal PTmap(%edx),%ecx
shrl $IDXSHIFT,%ecx
andb $0xfc,%cl
testb $PG_V,PTmap(%ecx) /* PTE page must be valid */
je 4f
movb PTmap(%edx),%dl
andb $PG_V|PG_RW|PG_U,%dl /* page must be valid and user writable */
cmpb $PG_V|PG_RW|PG_U,%dl
je 1f
4:
/* simulate a trap */
pushl %eax
call trapwrite
popl %edx /* remove junk parameter from stack */
testl %eax,%eax
jnz fusufault
1:
movl 4(%esp),%edx
#endif
2:
cmpl $VM_MAX_USER_ADDRESS-1,%edx /* verify address validity */
ja fusufault
sys/platform/vkernel/i386/cpu_regs.c
cr0 = rcr0();
cr0 |= CR0_NE; /* Done by npxinit() */
cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
#ifdef I386_CPU
if (cpu_class != CPUCLASS_386)
#endif
cr0 |= CR0_WP | CR0_AM;
cr0 |= CR0_WP | CR0_AM;
load_cr0(cr0);
load_gs(_udatasel);
#endif
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