DragonFlyBSD

static void hifn_intr(void *);

static u_int hifn_write_command(struct hifn_command *, u_int8_t *);

static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);

static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);

static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);

static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);

* always will allow the card to work. If a card is using the PCI

* bus clock and in a 33MHz slot then it will be operating at half

* speed until the correct information is provided.

*/

static void

hifn_getpllconfig(device_t dev, u_int *pll)

char *nxt;

if (resource_string_value("hifn", device_get_unit(dev),

fl = 33, fh = 66;

pllconfig = 0;

if (strncmp(pllspec, "ext", 3) == 0) {

bzero(sc, sizeof (*sc));

sc->sc_dev = dev;

/* XXX handle power management */

/*

* NB: Network code assumes we are blocked with splimp()

* so make sure the IRQ is marked appropriately.

*/

hifn_intr, sc,

&sc->sc_intrhand, NULL)) {

device_printf(dev, "could not setup interrupt\n");

hifn_init_pubrng(sc);

/* NB: 1 means the callout runs w/o Giant locked */

callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);

return (0);

fail_io0:

bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);

fail_pci:

return (ENXIO);

}

/* disable interrupts */

WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);

/*XXX other resources */

callout_stop(&sc->sc_tickto);

callout_stop(&sc->sc_rngto);

bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);

bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);

return (0);

}

else

sc->sc_rnghz = 1;

/* NB: 1 means the callout runs w/o Giant locked */

callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);

}

#endif

hifn_puc_wait(struct hifn_softc *sc)

{

int i;

for (i = 5000; i > 0; i--) {

DELAY(1);

break;

}

if (!i)

static void

hifn_reset_puc(struct hifn_softc *sc)

{

/* Reset processing unit */

hifn_puc_wait(sc);

}

}

if (reg == 1000)

kprintf(": cram init timeout\n");

}

}

/* turn off the clocks and insure bypass is set */

pll = READ_REG_1(sc, HIFN_1_PLL);

pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))

WRITE_REG_1(sc, HIFN_1_PLL, pll);

DELAY(10*1000); /* 10ms */

/* change configuration */

base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);

dlen >>= 16;

slen >>= 16;

base_cmd->session_num = htole16(

((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |

((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));

buf_pos += sizeof(hifn_base_command_t);

return (1);

}

static int

hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)

{

BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

used++;

}

if (cmd->sloplen == 0) {

BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

used++;

}

}

dma->dstr[idx].p = htole32(p);

HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

used++;

dma->dsti = idx;

dma->dstu += used;

return (idx);

}

static int

hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)

{

HIFN_SRCR_SYNC(sc, idx,

BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);

}

dma->srci = idx;

dma->srcu += src->nsegs;

int hint)

{

struct hifn_dma *dma = sc->sc_dma;

int cmdi, resi, err = 0;

/*

*

* NB: check this first since it's easy.

*/

if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE ||

(dma->resu + 1) > HIFN_D_RES_RSIZE) {

#ifdef HIFN_DEBUG

}

#endif

hifnstats.hst_nomem_cr++;

return (ERESTART);

}

if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {

hifnstats.hst_nomem_map++;

return (ENOMEM);

}

goto err_srcmap1;

}

} else if (crp->crp_flags & CRYPTO_F_IOV) {

cmd->src_io->uio_segflg = UIO_USERSPACE;

if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,

cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {

hifnstats.hst_nomem_load++;

goto err_dstmap1;

}

} else if (crp->crp_flags & CRYPTO_F_IOV) {

cmd->dst_io->uio_segflg |= UIO_USERSPACE;

if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,

cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {

hifnstats.hst_nomem_load++;

HIFN_CMDR_SYNC(sc, cmdi,

BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);

dma->cmdu++;

/*

* We don't worry about missing an interrupt (which a "command wait"

hifnstats.hst_ibytes += cmd->src_mapsize;

hifn_dmamap_load_src(sc, cmd);

/*

* Unlike other descriptors, we don't mask done interrupt from

HIFN_RESR_SYNC(sc, resi,

BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);

dma->resu++;

if (cmd->sloplen)

cmd->slopidx = resi;

hifn_dmamap_load_dst(sc, cmd);

if (sc->sc_d_busy == 0) {

sc->sc_d_busy = 1;

}

#ifdef HIFN_DEBUG

if (hifn_debug) {

#endif

sc->sc_active = 5;

KASSERT(err == 0, ("hifn_crypto: success with error %u", err));

return (err); /* success */

bus_dmamap_unload(sc->sc_dmat, cmd->src_map);

err_srcmap1:

bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);

return (err);

}

{

struct hifn_softc *sc = vsc;

if (sc->sc_active == 0) {

struct hifn_dma *dma = sc->sc_dma;

u_int32_t r = 0;

WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);

} else

sc->sc_active--;

callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);

}

return;

}

dma = sc->sc_dma;

#ifdef HIFN_DEBUG

device_printf(sc->sc_dev, "abort, resetting.\n");

hifnstats.hst_abort++;

hifn_abort(sc);

return;

}

}

dma->cmdk = i; dma->cmdu = u;

if (sc->sc_needwakeup) { /* XXX check high watermark */

int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);

#ifdef HIFN_DEBUG

* id on successful allocation.

*/

static int

{

struct cryptoini *c;

int mac = 0, cry = 0, sesn;

struct hifn_session *ses = NULL;

if (sidp == NULL || cri == NULL || sc == NULL)

return (EINVAL);

if (sc->sc_sessions == NULL) {

ses = sc->sc_sessions = (struct hifn_session *)kmalloc(

sizeof(*ses), M_DEVBUF, M_NOWAIT);

return (ENOMEM);

sesn = 0;

sc->sc_nsessions = 1;

} else {

sesn = sc->sc_nsessions;

ses = (struct hifn_session *)kmalloc((sesn + 1) *

sizeof(*ses), M_DEVBUF, M_NOWAIT);

return (ENOMEM);

bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));

bzero(sc->sc_sessions, sesn * sizeof(*ses));

kfree(sc->sc_sessions, M_DEVBUF);

sc->sc_nsessions++;

}

}

bzero(ses, sizeof(*ses));

ses->hs_used = 1;

break;

}

}

case CRYPTO_DES_CBC:

case CRYPTO_3DES_CBC:

case CRYPTO_AES_CBC:

#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff)

static int

{

u_int32_t sid = CRYPTO_SESID2LID(tid);

KASSERT(sc != NULL, ("hifn_freesession: null softc"));

if (sc == NULL)

return (EINVAL);

session = HIFN_SESSION(sid);

}

static int

{

struct hifn_command *cmd = NULL;

int session, err, ivlen;

struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;

if ((enccrd->crd_flags & CRD_F_IV_PRESENT)

== 0) {

}

} else {

if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)

bcopy(enccrd->crd_iv, cmd->iv, ivlen);

}

}

cmd->ck = enccrd->crd_key;

cmd->cklen = enccrd->crd_klen >> 3;

cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;

/*

* Need to specify the size for the AES key in the masks.

*/

}

if (cmd->sloplen != 0) {

}

i = dma->dstk; u = dma->dstu;

continue;

ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?

HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);

break;

}

}

crypto_copyback(crp->crp_flags, crp->crp_buf,

crd->crd_inject, len, macbuf);

break;

}

}

#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */

#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */

#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */

#define HIFN_0_SPACESIZE 0x20 /* Register space size */

/* Processing Unit Control Register (HIFN_0_PUCTRL) */

#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */

#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */

#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */

#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */

#define HIFN_1_REVID 0x98 /* Revision ID */

#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */

#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */

/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */

#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */

*/

struct hifn_softc {

device_t sc_dev; /* device backpointer */

bus_dma_tag_t sc_dmat; /* parent DMA tag decriptor */

struct resource *sc_bar0res;

bus_space_handle_t sc_sh0; /* bar0 bus space handle */

int sc_suspended;

};

/*

* hifn_command_t

*