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radeon47fast.patch

davshao, 04/26/2017 08:57 PM

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sys/conf/files
2172 2172
dev/drm/radeon/radeon_agp.c		optional radeon drm
2173 2173
dev/drm/radeon/radeon_asic.c		optional radeon drm
2174 2174
dev/drm/radeon/radeon_atombios.c	optional radeon drm
2175
dev/drm/radeon/radeon_audio.c		optional radeon drm
2175 2176
dev/drm/radeon/radeon_benchmark.c	optional radeon drm
2176 2177
dev/drm/radeon/radeon_bios.c		optional radeon drm
2177 2178
dev/drm/radeon/radeon_clocks.c		optional radeon drm
......
2181 2182
dev/drm/radeon/radeon_cursor.c		optional radeon drm
2182 2183
dev/drm/radeon/radeon_device.c		optional radeon drm
2183 2184
dev/drm/radeon/radeon_display.c		optional radeon drm
2185
dev/drm/radeon/radeon_dp_auxch.c	optional radeon drm
2184 2186
dev/drm/radeon/radeon_drv.c		optional radeon drm
2185 2187
dev/drm/radeon/radeon_encoders.c	optional radeon drm
2186 2188
dev/drm/radeon/radeon_fb.c		optional radeon drm
sys/dev/drm/radeon/Makefile
22 22
	radeon_agp.c							\
23 23
	radeon_asic.c							\
24 24
	radeon_atombios.c						\
25
	radeon_audio.c						\
25 26
	radeon_benchmark.c						\
26 27
	radeon_bios.c							\
27 28
	radeon_clocks.c							\
......
31 32
	radeon_cursor.c							\
32 33
	radeon_device.c							\
33 34
	radeon_display.c						\
35
	radeon_dp_auxch.c						\
34 36
	radeon_drv.c							\
35 37
	radeon_encoders.c						\
36 38
	radeon_fb.c							\
sys/dev/drm/radeon/atom.c
65 65
int atom_debug = 0;
66 66
static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
67 67

  
68
static uint32_t atom_arg_mask[8] =
69
    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
70
0xFF000000 };
68
static uint32_t atom_arg_mask[8] = {
69
	0xFFFFFFFF, 0x0000FFFF, 0x00FFFF00, 0xFFFF0000,
70
	0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000
71
};
71 72
static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
72 73

  
73 74
static int atom_dst_to_src[8][4] = {
......
91 92
		kprintf("   ");
92 93
}
93 94

  
94
#define ATOM_DEBUG_PRINT(...) do if (atom_debug) { kprintf(__FILE__ __VA_ARGS__); } while (0)
95
#define ATOM_SDEBUG_PRINT(...) do if (atom_debug) { kprintf(__FILE__); debug_print_spaces(debug_depth); kprintf(__VA_ARGS__); } while (0)
96
#else
97
#define ATOM_DEBUG_PRINT(...) do { } while (0)
98
#define ATOM_SDEBUG_PRINT(...) do { } while (0)
95
#ifdef DEBUG
96
#undef DEBUG
97
#endif
98
#ifdef SDEBUG
99
#undef SDEBUG
99 100
#endif
100 101

  
102
#define DEBUG(...) do if (atom_debug) { kprintf(__FILE__ __VA_ARGS__); } while (0)
103
#define SDEBUG(...) do if (atom_debug) { kprintf(__FILE__); debug_print_spaces(debug_depth); kprintf(__VA_ARGS__); } while (0)
104

  
105
#else /* !ATOM_DEBUG */
106

  
107
#define DEBUG(...) do { } while (0)
108
#define SDEBUG(...) do { } while (0)
109

  
110
#endif /* ATOM_DEBUG */
111

  
101 112
static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
102 113
				 uint32_t index, uint32_t data)
103 114
{
......
189 200
		idx = U16(*ptr);
190 201
		(*ptr) += 2;
191 202
		if (print)
192
			ATOM_DEBUG_PRINT("REG[0x%04X]", idx);
203
			DEBUG("REG[0x%04X]", idx);
193 204
		idx += gctx->reg_block;
194 205
		switch (gctx->io_mode) {
195 206
		case ATOM_IO_MM:
......
227 238
		 * tables, noticed on a DEC Alpha. */
228 239
		val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
229 240
		if (print)
230
			ATOM_DEBUG_PRINT("PS[0x%02X,0x%04X]", idx, val);
241
			DEBUG("PS[0x%02X,0x%04X]", idx, val);
231 242
		break;
232 243
	case ATOM_ARG_WS:
233 244
		idx = U8(*ptr);
234 245
		(*ptr)++;
235 246
		if (print)
236
			ATOM_DEBUG_PRINT("WS[0x%02X]", idx);
247
			DEBUG("WS[0x%02X]", idx);
237 248
		switch (idx) {
238 249
		case ATOM_WS_QUOTIENT:
239 250
			val = gctx->divmul[0];
......
271 282
		(*ptr) += 2;
272 283
		if (print) {
273 284
			if (gctx->data_block)
274
				ATOM_DEBUG_PRINT("ID[0x%04X+%04X]", idx, gctx->data_block);
285
				DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
275 286
			else
276
				ATOM_DEBUG_PRINT("ID[0x%04X]", idx);
287
				DEBUG("ID[0x%04X]", idx);
277 288
		}
278 289
		val = U32(idx + gctx->data_block);
279 290
		break;
......
287 298
		} else
288 299
			val = gctx->scratch[(gctx->fb_base / 4) + idx];
289 300
		if (print)
290
			ATOM_DEBUG_PRINT("FB[0x%02X]", idx);
301
			DEBUG("FB[0x%02X]", idx);
291 302
		break;
292 303
	case ATOM_ARG_IMM:
293 304
		switch (align) {
......
295 306
			val = U32(*ptr);
296 307
			(*ptr) += 4;
297 308
			if (print)
298
				ATOM_DEBUG_PRINT("IMM 0x%08X\n", val);
309
				DEBUG("IMM 0x%08X\n", val);
299 310
			return val;
300 311
		case ATOM_SRC_WORD0:
301 312
		case ATOM_SRC_WORD8:
......
303 314
			val = U16(*ptr);
304 315
			(*ptr) += 2;
305 316
			if (print)
306
				ATOM_DEBUG_PRINT("IMM 0x%04X\n", val);
317
				DEBUG("IMM 0x%04X\n", val);
307 318
			return val;
308 319
		case ATOM_SRC_BYTE0:
309 320
		case ATOM_SRC_BYTE8:
......
312 323
			val = U8(*ptr);
313 324
			(*ptr)++;
314 325
			if (print)
315
				ATOM_DEBUG_PRINT("IMM 0x%02X\n", val);
326
				DEBUG("IMM 0x%02X\n", val);
316 327
			return val;
317 328
		}
318 329
		return 0;
......
320 331
		idx = U8(*ptr);
321 332
		(*ptr)++;
322 333
		if (print)
323
			ATOM_DEBUG_PRINT("PLL[0x%02X]", idx);
334
			DEBUG("PLL[0x%02X]", idx);
324 335
		val = gctx->card->pll_read(gctx->card, idx);
325 336
		break;
326 337
	case ATOM_ARG_MC:
327 338
		idx = U8(*ptr);
328 339
		(*ptr)++;
329 340
		if (print)
330
			ATOM_DEBUG_PRINT("MC[0x%02X]", idx);
341
			DEBUG("MC[0x%02X]", idx);
331 342
		val = gctx->card->mc_read(gctx->card, idx);
332 343
		break;
333 344
	}
......
338 349
	if (print)
339 350
		switch (align) {
340 351
		case ATOM_SRC_DWORD:
341
			ATOM_DEBUG_PRINT(".[31:0] -> 0x%08X\n", val);
352
			DEBUG(".[31:0] -> 0x%08X\n", val);
342 353
			break;
343 354
		case ATOM_SRC_WORD0:
344
			ATOM_DEBUG_PRINT(".[15:0] -> 0x%04X\n", val);
355
			DEBUG(".[15:0] -> 0x%04X\n", val);
345 356
			break;
346 357
		case ATOM_SRC_WORD8:
347
			ATOM_DEBUG_PRINT(".[23:8] -> 0x%04X\n", val);
358
			DEBUG(".[23:8] -> 0x%04X\n", val);
348 359
			break;
349 360
		case ATOM_SRC_WORD16:
350
			ATOM_DEBUG_PRINT(".[31:16] -> 0x%04X\n", val);
361
			DEBUG(".[31:16] -> 0x%04X\n", val);
351 362
			break;
352 363
		case ATOM_SRC_BYTE0:
353
			ATOM_DEBUG_PRINT(".[7:0] -> 0x%02X\n", val);
364
			DEBUG(".[7:0] -> 0x%02X\n", val);
354 365
			break;
355 366
		case ATOM_SRC_BYTE8:
356
			ATOM_DEBUG_PRINT(".[15:8] -> 0x%02X\n", val);
367
			DEBUG(".[15:8] -> 0x%02X\n", val);
357 368
			break;
358 369
		case ATOM_SRC_BYTE16:
359
			ATOM_DEBUG_PRINT(".[23:16] -> 0x%02X\n", val);
370
			DEBUG(".[23:16] -> 0x%02X\n", val);
360 371
			break;
361 372
		case ATOM_SRC_BYTE24:
362
			ATOM_DEBUG_PRINT(".[31:24] -> 0x%02X\n", val);
373
			DEBUG(".[31:24] -> 0x%02X\n", val);
363 374
			break;
364 375
		}
365 376
	return val;
......
464 475
	case ATOM_ARG_REG:
465 476
		idx = U16(*ptr);
466 477
		(*ptr) += 2;
467
		ATOM_DEBUG_PRINT("REG[0x%04X]", idx);
478
		DEBUG("REG[0x%04X]", idx);
468 479
		idx += gctx->reg_block;
469 480
		switch (gctx->io_mode) {
470 481
		case ATOM_IO_MM:
......
500 511
	case ATOM_ARG_PS:
501 512
		idx = U8(*ptr);
502 513
		(*ptr)++;
503
		ATOM_DEBUG_PRINT("PS[0x%02X]", idx);
514
		DEBUG("PS[0x%02X]", idx);
504 515
		ctx->ps[idx] = cpu_to_le32(val);
505 516
		break;
506 517
	case ATOM_ARG_WS:
507 518
		idx = U8(*ptr);
508 519
		(*ptr)++;
509
		ATOM_DEBUG_PRINT("WS[0x%02X]", idx);
520
		DEBUG("WS[0x%02X]", idx);
510 521
		switch (idx) {
511 522
		case ATOM_WS_QUOTIENT:
512 523
			gctx->divmul[0] = val;
......
544 555
				  gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
545 556
		} else
546 557
			gctx->scratch[(gctx->fb_base / 4) + idx] = val;
547
		ATOM_DEBUG_PRINT("FB[0x%02X]", idx);
558
		DEBUG("FB[0x%02X]", idx);
548 559
		break;
549 560
	case ATOM_ARG_PLL:
550 561
		idx = U8(*ptr);
551 562
		(*ptr)++;
552
		ATOM_DEBUG_PRINT("PLL[0x%02X]", idx);
563
		DEBUG("PLL[0x%02X]", idx);
553 564
		gctx->card->pll_write(gctx->card, idx, val);
554 565
		break;
555 566
	case ATOM_ARG_MC:
556 567
		idx = U8(*ptr);
557 568
		(*ptr)++;
558
		ATOM_DEBUG_PRINT("MC[0x%02X]", idx);
569
		DEBUG("MC[0x%02X]", idx);
559 570
		gctx->card->mc_write(gctx->card, idx, val);
560 571
		return;
561 572
	}
562 573
	switch (align) {
563 574
	case ATOM_SRC_DWORD:
564
		ATOM_DEBUG_PRINT(".[31:0] <- 0x%08X\n", old_val);
575
		DEBUG(".[31:0] <- 0x%08X\n", old_val);
565 576
		break;
566 577
	case ATOM_SRC_WORD0:
567
		ATOM_DEBUG_PRINT(".[15:0] <- 0x%04X\n", old_val);
578
		DEBUG(".[15:0] <- 0x%04X\n", old_val);
568 579
		break;
569 580
	case ATOM_SRC_WORD8:
570
		ATOM_DEBUG_PRINT(".[23:8] <- 0x%04X\n", old_val);
581
		DEBUG(".[23:8] <- 0x%04X\n", old_val);
571 582
		break;
572 583
	case ATOM_SRC_WORD16:
573
		ATOM_DEBUG_PRINT(".[31:16] <- 0x%04X\n", old_val);
584
		DEBUG(".[31:16] <- 0x%04X\n", old_val);
574 585
		break;
575 586
	case ATOM_SRC_BYTE0:
576
		ATOM_DEBUG_PRINT(".[7:0] <- 0x%02X\n", old_val);
587
		DEBUG(".[7:0] <- 0x%02X\n", old_val);
577 588
		break;
578 589
	case ATOM_SRC_BYTE8:
579
		ATOM_DEBUG_PRINT(".[15:8] <- 0x%02X\n", old_val);
590
		DEBUG(".[15:8] <- 0x%02X\n", old_val);
580 591
		break;
581 592
	case ATOM_SRC_BYTE16:
582
		ATOM_DEBUG_PRINT(".[23:16] <- 0x%02X\n", old_val);
593
		DEBUG(".[23:16] <- 0x%02X\n", old_val);
583 594
		break;
584 595
	case ATOM_SRC_BYTE24:
585
		ATOM_DEBUG_PRINT(".[31:24] <- 0x%02X\n", old_val);
596
		DEBUG(".[31:24] <- 0x%02X\n", old_val);
586 597
		break;
587 598
	}
588 599
}
......
592 603
	uint8_t attr = U8((*ptr)++);
593 604
	uint32_t dst, src, saved;
594 605
	int dptr = *ptr;
595
	ATOM_SDEBUG_PRINT("   dst: ");
606
	SDEBUG("   dst: ");
596 607
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
597
	ATOM_SDEBUG_PRINT("   src: ");
608
	SDEBUG("   src: ");
598 609
	src = atom_get_src(ctx, attr, ptr);
599 610
	dst += src;
600
	ATOM_SDEBUG_PRINT("   dst: ");
611
	SDEBUG("   dst: ");
601 612
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
602 613
}
603 614

  
......
606 617
	uint8_t attr = U8((*ptr)++);
607 618
	uint32_t dst, src, saved;
608 619
	int dptr = *ptr;
609
	ATOM_SDEBUG_PRINT("   dst: ");
620
	SDEBUG("   dst: ");
610 621
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
611
	ATOM_SDEBUG_PRINT("   src: ");
622
	SDEBUG("   src: ");
612 623
	src = atom_get_src(ctx, attr, ptr);
613 624
	dst &= src;
614
	ATOM_SDEBUG_PRINT("   dst: ");
625
	SDEBUG("   dst: ");
615 626
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
616 627
}
617 628

  
......
626 637
	int r = 0;
627 638

  
628 639
	if (idx < ATOM_TABLE_NAMES_CNT)
629
		ATOM_SDEBUG_PRINT("   table: %d (%s)\n", idx, atom_table_names[idx]);
640
		SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
630 641
	else
631
		ATOM_SDEBUG_PRINT("   table: %d\n", idx);
642
		SDEBUG("   table: %d\n", idx);
632 643
	if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
633 644
		r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
634 645
	if (r) {
......
644 655
	attr &= 0x38;
645 656
	attr |= atom_def_dst[attr >> 3] << 6;
646 657
	atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
647
	ATOM_SDEBUG_PRINT("   dst: ");
658
	SDEBUG("   dst: ");
648 659
	atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
649 660
}
650 661

  
......
652 663
{
653 664
	uint8_t attr = U8((*ptr)++);
654 665
	uint32_t dst, src;
655
	ATOM_SDEBUG_PRINT("   src1: ");
666
	SDEBUG("   src1: ");
656 667
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
657
	ATOM_SDEBUG_PRINT("   src2: ");
668
	SDEBUG("   src2: ");
658 669
	src = atom_get_src(ctx, attr, ptr);
659 670
	ctx->ctx->cs_equal = (dst == src);
660 671
	ctx->ctx->cs_above = (dst > src);
661
	ATOM_SDEBUG_PRINT("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
672
	SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
662 673
	       ctx->ctx->cs_above ? "GT" : "LE");
663 674
}
664 675

  
665 676
static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
666 677
{
667 678
	unsigned count = U8((*ptr)++);
668
	ATOM_SDEBUG_PRINT("   count: %d\n", count);
679
	SDEBUG("   count: %d\n", count);
669 680
	if (arg == ATOM_UNIT_MICROSEC)
670 681
		udelay(count);
671 682
	else if (!drm_can_sleep())
......
678 689
{
679 690
	uint8_t attr = U8((*ptr)++);
680 691
	uint32_t dst, src;
681
	ATOM_SDEBUG_PRINT("   src1: ");
692
	SDEBUG("   src1: ");
682 693
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
683
	ATOM_SDEBUG_PRINT("   src2: ");
694
	SDEBUG("   src2: ");
684 695
	src = atom_get_src(ctx, attr, ptr);
685 696
	if (src != 0) {
686 697
		ctx->ctx->divmul[0] = dst / src;
......
726 737
		break;
727 738
	}
728 739
	if (arg != ATOM_COND_ALWAYS)
729
		ATOM_SDEBUG_PRINT("   taken: %s\n", execute ? "yes" : "no");
730
	ATOM_SDEBUG_PRINT("   target: 0x%04X\n", target);
740
		SDEBUG("   taken: %s\n", execute ? "yes" : "no");
741
	SDEBUG("   target: 0x%04X\n", target);
731 742
	if (execute) {
732 743
		if (ctx->last_jump == (ctx->start + target)) {
733 744
			cjiffies = jiffies;
......
754 765
	uint8_t attr = U8((*ptr)++);
755 766
	uint32_t dst, mask, src, saved;
756 767
	int dptr = *ptr;
757
	ATOM_SDEBUG_PRINT("   dst: ");
768
	SDEBUG("   dst: ");
758 769
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
759 770
	mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
760
	ATOM_SDEBUG_PRINT("   mask: 0x%08x", mask);
761
	ATOM_SDEBUG_PRINT("   src: ");
771
	SDEBUG("   mask: 0x%08x", mask);
772
	SDEBUG("   src: ");
762 773
	src = atom_get_src(ctx, attr, ptr);
763 774
	dst &= mask;
764 775
	dst |= src;
765
	ATOM_SDEBUG_PRINT("   dst: ");
776
	SDEBUG("   dst: ");
766 777
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
767 778
}
768 779

  
......
777 788
		atom_skip_dst(ctx, arg, attr, ptr);
778 789
		saved = 0xCDCDCDCD;
779 790
	}
780
	ATOM_SDEBUG_PRINT("   src: ");
791
	SDEBUG("   src: ");
781 792
	src = atom_get_src(ctx, attr, ptr);
782
	ATOM_SDEBUG_PRINT("   dst: ");
793
	SDEBUG("   dst: ");
783 794
	atom_put_dst(ctx, arg, attr, &dptr, src, saved);
784 795
}
785 796

  
......
787 798
{
788 799
	uint8_t attr = U8((*ptr)++);
789 800
	uint32_t dst, src;
790
	ATOM_SDEBUG_PRINT("   src1: ");
801
	SDEBUG("   src1: ");
791 802
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
792
	ATOM_SDEBUG_PRINT("   src2: ");
803
	SDEBUG("   src2: ");
793 804
	src = atom_get_src(ctx, attr, ptr);
794 805
	ctx->ctx->divmul[0] = dst * src;
795 806
}
......
804 815
	uint8_t attr = U8((*ptr)++);
805 816
	uint32_t dst, src, saved;
806 817
	int dptr = *ptr;
807
	ATOM_SDEBUG_PRINT("   dst: ");
818
	SDEBUG("   dst: ");
808 819
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
809
	ATOM_SDEBUG_PRINT("   src: ");
820
	SDEBUG("   src: ");
810 821
	src = atom_get_src(ctx, attr, ptr);
811 822
	dst |= src;
812
	ATOM_SDEBUG_PRINT("   dst: ");
823
	SDEBUG("   dst: ");
813 824
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
814 825
}
815 826

  
816 827
static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
817 828
{
818 829
	uint8_t val = U8((*ptr)++);
819
	ATOM_SDEBUG_PRINT("POST card output: 0x%02X\n", val);
830
	SDEBUG("POST card output: 0x%02X\n", val);
820 831
}
821 832

  
822 833
static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
......
838 849
{
839 850
	int idx = U8(*ptr);
840 851
	(*ptr)++;
841
	ATOM_SDEBUG_PRINT("   block: %d\n", idx);
852
	SDEBUG("   block: %d\n", idx);
842 853
	if (!idx)
843 854
		ctx->ctx->data_block = 0;
844 855
	else if (idx == 255)
845 856
		ctx->ctx->data_block = ctx->start;
846 857
	else
847 858
		ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
848
	ATOM_SDEBUG_PRINT("   base: 0x%04X\n", ctx->ctx->data_block);
859
	SDEBUG("   base: 0x%04X\n", ctx->ctx->data_block);
849 860
}
850 861

  
851 862
static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
852 863
{
853 864
	uint8_t attr = U8((*ptr)++);
854
	ATOM_SDEBUG_PRINT("   fb_base: ");
865
	SDEBUG("   fb_base: ");
855 866
	ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
856 867
}
857 868

  
......
862 873
	case ATOM_PORT_ATI:
863 874
		port = U16(*ptr);
864 875
		if (port < ATOM_IO_NAMES_CNT)
865
			ATOM_SDEBUG_PRINT("   port: %d (%s)\n", port, atom_io_names[port]);
876
			SDEBUG("   port: %d (%s)\n", port, atom_io_names[port]);
866 877
		else
867
			ATOM_SDEBUG_PRINT("   port: %d\n", port);
878
			SDEBUG("   port: %d\n", port);
868 879
		if (!port)
869 880
			ctx->ctx->io_mode = ATOM_IO_MM;
870 881
		else
......
886 897
{
887 898
	ctx->ctx->reg_block = U16(*ptr);
888 899
	(*ptr) += 2;
889
	ATOM_SDEBUG_PRINT("   base: 0x%04X\n", ctx->ctx->reg_block);
900
	SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
890 901
}
891 902

  
892 903
static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
......
896 907
	int dptr = *ptr;
897 908
	attr &= 0x38;
898 909
	attr |= atom_def_dst[attr >> 3] << 6;
899
	ATOM_SDEBUG_PRINT("   dst: ");
910
	SDEBUG("   dst: ");
900 911
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
901 912
	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
902
	ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
913
	SDEBUG("   shift: %d\n", shift);
903 914
	dst <<= shift;
904
	ATOM_SDEBUG_PRINT("   dst: ");
915
	SDEBUG("   dst: ");
905 916
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
906 917
}
907 918

  
......
912 923
	int dptr = *ptr;
913 924
	attr &= 0x38;
914 925
	attr |= atom_def_dst[attr >> 3] << 6;
915
	ATOM_SDEBUG_PRINT("   dst: ");
926
	SDEBUG("   dst: ");
916 927
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
917 928
	shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
918
	ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
929
	SDEBUG("   shift: %d\n", shift);
919 930
	dst >>= shift;
920
	ATOM_SDEBUG_PRINT("   dst: ");
931
	SDEBUG("   dst: ");
921 932
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
922 933
}
923 934

  
......
927 938
	uint32_t saved, dst;
928 939
	int dptr = *ptr;
929 940
	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
930
	ATOM_SDEBUG_PRINT("   dst: ");
941
	SDEBUG("   dst: ");
931 942
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
932 943
	/* op needs to full dst value */
933 944
	dst = saved;
934 945
	shift = atom_get_src(ctx, attr, ptr);
935
	ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
946
	SDEBUG("   shift: %d\n", shift);
936 947
	dst <<= shift;
937 948
	dst &= atom_arg_mask[dst_align];
938 949
	dst >>= atom_arg_shift[dst_align];
939
	ATOM_SDEBUG_PRINT("   dst: ");
950
	SDEBUG("   dst: ");
940 951
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
941 952
}
942 953

  
......
946 957
	uint32_t saved, dst;
947 958
	int dptr = *ptr;
948 959
	uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
949
	ATOM_SDEBUG_PRINT("   dst: ");
960
	SDEBUG("   dst: ");
950 961
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
951 962
	/* op needs to full dst value */
952 963
	dst = saved;
953 964
	shift = atom_get_src(ctx, attr, ptr);
954
	ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
965
	SDEBUG("   shift: %d\n", shift);
955 966
	dst >>= shift;
956 967
	dst &= atom_arg_mask[dst_align];
957 968
	dst >>= atom_arg_shift[dst_align];
958
	ATOM_SDEBUG_PRINT("   dst: ");
969
	SDEBUG("   dst: ");
959 970
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
960 971
}
961 972

  
......
964 975
	uint8_t attr = U8((*ptr)++);
965 976
	uint32_t dst, src, saved;
966 977
	int dptr = *ptr;
967
	ATOM_SDEBUG_PRINT("   dst: ");
978
	SDEBUG("   dst: ");
968 979
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
969
	ATOM_SDEBUG_PRINT("   src: ");
980
	SDEBUG("   src: ");
970 981
	src = atom_get_src(ctx, attr, ptr);
971 982
	dst -= src;
972
	ATOM_SDEBUG_PRINT("   dst: ");
983
	SDEBUG("   dst: ");
973 984
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
974 985
}
975 986

  
......
977 988
{
978 989
	uint8_t attr = U8((*ptr)++);
979 990
	uint32_t src, val, target;
980
	ATOM_SDEBUG_PRINT("   switch: ");
991
	SDEBUG("   switch: ");
981 992
	src = atom_get_src(ctx, attr, ptr);
982 993
	while (U16(*ptr) != ATOM_CASE_END)
983 994
		if (U8(*ptr) == ATOM_CASE_MAGIC) {
984 995
			(*ptr)++;
985
			ATOM_SDEBUG_PRINT("   case: ");
996
			SDEBUG("   case: ");
986 997
			val =
987 998
			    atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
988 999
					 ptr);
989 1000
			target = U16(*ptr);
990 1001
			if (val == src) {
991
				ATOM_SDEBUG_PRINT("   target: %04X\n", target);
1002
				SDEBUG("   target: %04X\n", target);
992 1003
				*ptr = ctx->start + target;
993 1004
				return;
994 1005
			}
......
1004 1015
{
1005 1016
	uint8_t attr = U8((*ptr)++);
1006 1017
	uint32_t dst, src;
1007
	ATOM_SDEBUG_PRINT("   src1: ");
1018
	SDEBUG("   src1: ");
1008 1019
	dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1009
	ATOM_SDEBUG_PRINT("   src2: ");
1020
	SDEBUG("   src2: ");
1010 1021
	src = atom_get_src(ctx, attr, ptr);
1011 1022
	ctx->ctx->cs_equal = ((dst & src) == 0);
1012
	ATOM_SDEBUG_PRINT("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1023
	SDEBUG("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1013 1024
}
1014 1025

  
1015 1026
static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
......
1017 1028
	uint8_t attr = U8((*ptr)++);
1018 1029
	uint32_t dst, src, saved;
1019 1030
	int dptr = *ptr;
1020
	ATOM_SDEBUG_PRINT("   dst: ");
1031
	SDEBUG("   dst: ");
1021 1032
	dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1022
	ATOM_SDEBUG_PRINT("   src: ");
1033
	SDEBUG("   src: ");
1023 1034
	src = atom_get_src(ctx, attr, ptr);
1024 1035
	dst ^= src;
1025
	ATOM_SDEBUG_PRINT("   dst: ");
1036
	SDEBUG("   dst: ");
1026 1037
	atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1027 1038
}
1028 1039

  
......
1175 1186
	ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1176 1187
	ptr = base + ATOM_CT_CODE_PTR;
1177 1188

  
1178
	ATOM_SDEBUG_PRINT(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1189
	SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1179 1190

  
1180 1191
	ectx.ctx = ctx;
1181 1192
	ectx.ps_shift = ps / 4;
......
1192 1203
	while (1) {
1193 1204
		op = CU8(ptr++);
1194 1205
		if (op < ATOM_OP_NAMES_CNT)
1195
			ATOM_SDEBUG_PRINT("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1206
			SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1196 1207
		else
1197
			ATOM_SDEBUG_PRINT("[%d] @ 0x%04X\n", op, ptr - 1);
1208
			SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
1198 1209
		if (ectx.abort) {
1199 1210
			DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1200 1211
				base, len, ws, ps, ptr - 1);
......
1212 1223
			break;
1213 1224
	}
1214 1225
	debug_depth--;
1215
	ATOM_SDEBUG_PRINT("<<\n");
1226
	SDEBUG("<<\n");
1216 1227

  
1217 1228
free:
1218 1229
	if (ws)
......
1224 1235
{
1225 1236
	int r;
1226 1237

  
1227
	lockmgr(&ctx->mutex, LK_EXCLUSIVE);
1238
	mutex_lock(&ctx->mutex);
1228 1239
	/* reset data block */
1229 1240
	ctx->data_block = 0;
1230 1241
	/* reset reg block */
......
1237 1248
	ctx->divmul[0] = 0;
1238 1249
	ctx->divmul[1] = 0;
1239 1250
	r = atom_execute_table_locked(ctx, index, params);
1240
	lockmgr(&ctx->mutex, LK_RELEASE);
1251
	mutex_unlock(&ctx->mutex);
1241 1252
	return r;
1242 1253
}
1243 1254

  
1244 1255
int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1245 1256
{
1246 1257
	int r;
1247
	lockmgr(&ctx->scratch_mutex, LK_EXCLUSIVE);
1258
	mutex_lock(&ctx->scratch_mutex);
1248 1259
	r = atom_execute_table_scratch_unlocked(ctx, index, params);
1249
	lockmgr(&ctx->scratch_mutex, LK_RELEASE);
1260
	mutex_unlock(&ctx->scratch_mutex);
1250 1261
	return r;
1251 1262
}
1252 1263

  
sys/dev/drm/radeon/atombios.h
7944 7944
typedef struct {
7945 7945
  AMD_ACPI_DESCRIPTION_HEADER SHeader;
7946 7946
  UCHAR TableUUID[16];    //0x24
7947
  ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
7948
  ULONG Lib1ImageOffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
7947
  ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the structure.
7948
  ULONG Lib1ImageOffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the structure.
7949 7949
  ULONG Reserved[4];      //0x3C
7950 7950
}UEFI_ACPI_VFCT;
7951 7951

  
sys/dev/drm/radeon/atombios_crtc.c
275 275
		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 276
			atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 277
		atombios_blank_crtc(crtc, ATOM_DISABLE);
278
		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
278
		if (dev->num_crtcs > radeon_crtc->crtc_id)
279
			drm_vblank_on(dev, radeon_crtc->crtc_id);
279 280
		radeon_crtc_load_lut(crtc);
280 281
		break;
281 282
	case DRM_MODE_DPMS_STANDBY:
282 283
	case DRM_MODE_DPMS_SUSPEND:
283 284
	case DRM_MODE_DPMS_OFF:
284
		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
285
		if (dev->num_crtcs > radeon_crtc->crtc_id)
286
			drm_vblank_off(dev, radeon_crtc->crtc_id);
285 287
		if (radeon_crtc->enabled)
286 288
			atombios_blank_crtc(crtc, ATOM_ENABLE);
287 289
		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
......
331 333
		misc |= ATOM_COMPOSITESYNC;
332 334
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
333 335
		misc |= ATOM_INTERLACE;
336
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
337
 		misc |= ATOM_DOUBLE_CLOCK_MODE;
334 338
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
335
		misc |= ATOM_DOUBLE_CLOCK_MODE;
339
		misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
336 340

  
337 341
	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
338 342
	args.ucCRTC = radeon_crtc->crtc_id;
......
375 379
		misc |= ATOM_COMPOSITESYNC;
376 380
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
377 381
		misc |= ATOM_INTERLACE;
382
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
383
 		misc |= ATOM_DOUBLE_CLOCK_MODE;
378 384
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
379
		misc |= ATOM_DOUBLE_CLOCK_MODE;
385
		misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
380 386

  
381 387
	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
382 388
	args.ucCRTC = radeon_crtc->crtc_id;
......
583 589
		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
584 590
			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
585 591
		/* use frac fb div on RS780/RS880 */
586
		if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
592
		if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
593
		    && !radeon_crtc->ss_enabled)
587 594
			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
588 595
		if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
589 596
			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
......
613 620
			if (radeon_crtc->ss.refdiv) {
614 621
				radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
615 622
				radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
616
				if (ASIC_IS_AVIVO(rdev))
623
				if (ASIC_IS_AVIVO(rdev) &&
624
				    rdev->family != CHIP_RS780 &&
625
				    rdev->family != CHIP_RS880)
617 626
					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
618 627
			}
619 628
		}
......
1360 1369
		break;
1361 1370
	}
1362 1371

  
1372
	/* Make sure surface address is updated at vertical blank rather than
1373
	 * horizontal blank
1374
	 */
1375
	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1376

  
1363 1377
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1364 1378
	       upper_32_bits(fb_location));
1365 1379
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
......
1406 1420
	       (x << 16) | y);
1407 1421
	viewport_w = crtc->mode.hdisplay;
1408 1422
	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1423
	if ((rdev->family >= CHIP_BONAIRE) &&
1424
	    (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1425
		viewport_h *= 2;
1409 1426
	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1410 1427
	       (viewport_w << 16) | viewport_h);
1411 1428

  
1412
	/* pageflip setup */
1413
	/* make sure flip is at vb rather than hb */
1414
	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1415
	tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1416
	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1417

  
1418 1429
	/* set pageflip to happen only at start of vblank interval (front porch) */
1419 1430
	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1420 1431

  
......
1448 1459
	uint64_t fb_location;
1449 1460
	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1450 1461
	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1451
	u32 tmp, viewport_w, viewport_h;
1462
	u32 viewport_w, viewport_h;
1452 1463
	int r;
1453 1464
	bool bypass_lut = false;
1454 1465

  
......
1563 1574
	else
1564 1575
		WREG32(AVIVO_D2VGA_CONTROL, 0);
1565 1576

  
1577
	/* Make sure surface address is update at vertical blank rather than
1578
	 * horizontal blank
1579
	 */
1580
	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1581

  
1566 1582
	if (rdev->family >= CHIP_RV770) {
1567 1583
		if (radeon_crtc->crtc_id) {
1568 1584
			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
......
1609 1625
	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1610 1626
	       (viewport_w << 16) | viewport_h);
1611 1627

  
1612
	/* pageflip setup */
1613
	/* make sure flip is at vb rather than hb */
1614
	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1615
	tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1616
	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1617

  
1618 1628
	/* set pageflip to happen only at start of vblank interval (front porch) */
1619 1629
	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1620 1630

  
......
1724 1734
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1725 1735
{
1726 1736
	struct drm_device *dev = crtc->dev;
1737
	struct radeon_device *rdev = dev->dev_private;
1727 1738
	struct drm_crtc *test_crtc;
1728 1739
	struct radeon_crtc *test_radeon_crtc;
1729 1740

  
......
1733 1744
		test_radeon_crtc = to_radeon_crtc(test_crtc);
1734 1745
		if (test_radeon_crtc->encoder &&
1735 1746
		    ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1747
			/* PPLL2 is exclusive to UNIPHYA on DCE61 */
1748
			if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1749
			    test_radeon_crtc->pll_id == ATOM_PPLL2)
1750
				continue;
1736 1751
			/* for DP use the same PLL for all */
1737 1752
			if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1738 1753
				return test_radeon_crtc->pll_id;
......
1754 1769
{
1755 1770
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1756 1771
	struct drm_device *dev = crtc->dev;
1772
	struct radeon_device *rdev = dev->dev_private;
1757 1773
	struct drm_crtc *test_crtc;
1758 1774
	struct radeon_crtc *test_radeon_crtc;
1759 1775
	u32 adjusted_clock, test_adjusted_clock;
......
1769 1785
		test_radeon_crtc = to_radeon_crtc(test_crtc);
1770 1786
		if (test_radeon_crtc->encoder &&
1771 1787
		    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1788
			/* PPLL2 is exclusive to UNIPHYA on DCE61 */
1789
			if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1790
			    test_radeon_crtc->pll_id == ATOM_PPLL2)
1791
				continue;
1772 1792
			/* check if we are already driving this connector with another crtc */
1773 1793
			if (test_radeon_crtc->connector == radeon_crtc->connector) {
1774 1794
				/* if we are, return that pll */
......
1852 1872
				return pll;
1853 1873
		}
1854 1874
		/* otherwise, pick one of the plls */
1855
		if ((rdev->family == CHIP_KAVERI) ||
1856
		    (rdev->family == CHIP_KABINI) ||
1857
		    (rdev->family == CHIP_MULLINS)) {
1858
			/* KB/KV/ML has PPLL1 and PPLL2 */
1875
		if ((rdev->family == CHIP_KABINI) ||
1876
 		    (rdev->family == CHIP_MULLINS)) {
1877
			/* KB/ML has PPLL1 and PPLL2 */
1859 1878
			pll_in_use = radeon_get_pll_use_mask(crtc);
1860 1879
			if (!(pll_in_use & (1 << ATOM_PPLL2)))
1861 1880
				return ATOM_PPLL2;
......
1864 1883
			DRM_ERROR("unable to allocate a PPLL\n");
1865 1884
			return ATOM_PPLL_INVALID;
1866 1885
		} else {
1867
			/* CI has PPLL0, PPLL1, and PPLL2 */
1886
			/* CI/KV has PPLL0, PPLL1, and PPLL2 */
1868 1887
			pll_in_use = radeon_get_pll_use_mask(crtc);
1869 1888
			if (!(pll_in_use & (1 << ATOM_PPLL2)))
1870 1889
				return ATOM_PPLL2;
......
2040 2059
	atombios_crtc_set_base(crtc, x, y, old_fb);
2041 2060
	atombios_overscan_setup(crtc, mode, adjusted_mode);
2042 2061
	atombios_scaler_setup(crtc);
2062
	radeon_cursor_reset(crtc);
2043 2063
	/* update the hw version fpr dpm */
2044 2064
	radeon_crtc->hw_mode = *adjusted_mode;
2045 2065

  
......
2067 2087
		radeon_crtc->connector = NULL;
2068 2088
		return false;
2069 2089
	}
2090
	if (radeon_crtc->encoder) {
2091
		struct radeon_encoder *radeon_encoder =
2092
			to_radeon_encoder(radeon_crtc->encoder);
2093

  
2094
		radeon_crtc->output_csc = radeon_encoder->output_csc;
2095
	}
2070 2096
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2071 2097
		return false;
2072 2098
	if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
......
2155 2181
	case ATOM_PPLL0:
2156 2182
		/* disable the ppll */
2157 2183
		if ((rdev->family == CHIP_ARUBA) ||
2184
		    (rdev->family == CHIP_KAVERI) ||
2158 2185
		    (rdev->family == CHIP_BONAIRE) ||
2159 2186
		    (rdev->family == CHIP_HAWAII))
2160 2187
			atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
sys/dev/drm/radeon/atombios_dp.c
99 99

  
100 100
	memset(&args, 0, sizeof(args));
101 101

  
102
	lockmgr(&chan->mutex, LK_EXCLUSIVE);
103
	lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_EXCLUSIVE);
102
	mutex_lock(&chan->mutex);
103
	mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
104 104

  
105 105
	base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
106 106

  
......
148 148

  
149 149
	r = recv_bytes;
150 150
done:
151
	lockmgr(&rdev->mode_info.atom_context->scratch_mutex, LK_RELEASE);
152
	lockmgr(&chan->mutex, LK_RELEASE);
151
	mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
152
	mutex_unlock(&chan->mutex);
153 153

  
154 154
	return r;
155 155
}
......
158 158
#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
159 159

  
160 160
static ssize_t
161
radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
161
radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
162 162
{
163 163
	struct radeon_i2c_chan *chan =
164 164
		container_of(aux, struct radeon_i2c_chan, aux);
......
171 171
		return -E2BIG;
172 172

  
173 173
	tx_buf[0] = msg->address & 0xff;
174
	tx_buf[1] = msg->address >> 8;
175
	tx_buf[2] = msg->request << 4;
174
	tx_buf[1] = (msg->address >> 8) & 0xff;
175
	tx_buf[2] = (msg->request << 4) |
176
		((msg->address >> 16) & 0xf);
176 177
	tx_buf[3] = msg->size ? (msg->size - 1) : 0;
177 178

  
178 179
	switch (msg->request & ~DP_AUX_I2C_MOT) {
179 180
	case DP_AUX_NATIVE_WRITE:
180 181
	case DP_AUX_I2C_WRITE:
182
	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
183
		/* The atom implementation only supports writes with a max payload of
184
		 * 12 bytes since it uses 4 bits for the total count (header + payload)
185
		 * in the parameter space.  The atom interface supports 16 byte
186
		 * payloads for reads. The hw itself supports up to 16 bytes of payload.
187
		 */
188
		if (WARN_ON_ONCE(msg->size > 12))
189
			return -E2BIG;
181 190
		/* tx_size needs to be 4 even for bare address packets since the atom
182 191
		 * table needs the info in tx_buf[3].
183 192
		 */
......
219 228

  
220 229
void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
221 230
{
222
	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
223

  
224
	dig_connector->dp_i2c_bus->rec.hpd = radeon_connector->hpd.hpd;	/* XXX check*/
225
	dig_connector->dp_i2c_bus->aux.dev = radeon_connector->base.kdev;
226
	dig_connector->dp_i2c_bus->aux.transfer = radeon_dp_aux_transfer;
227
}
228

  
229
int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
230
{
231
	struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev);
232
	struct radeon_i2c_chan *auxch = algo_data->priv;
233
	u16 address = algo_data->address;
234
	u8 msg[5];
235
	u8 reply[2];
236
	unsigned retry;
237
	int msg_bytes;
238
	int reply_bytes = 1;
239
	int ret;
240
	u8 ack;
241

  
242
	/* Set up the address */
243
	msg[0] = address;
244
	msg[1] = address >> 8;
245

  
246
	/* Set up the command byte */
247
	if (mode & MODE_I2C_READ) {
248
		msg[2] = DP_AUX_I2C_READ << 4;
249
		msg_bytes = 4;
250
		msg[3] = msg_bytes << 4;
231
	struct drm_device *dev = radeon_connector->base.dev;
232
	struct radeon_device *rdev = dev->dev_private;
233
 	int ret;
234
 
235
 	radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
236
 	radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
237
	if (ASIC_IS_DCE5(rdev)) {
238
		if (radeon_auxch)
239
			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
240
		else
241
			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
251 242
	} else {
252
		msg[2] = DP_AUX_I2C_WRITE << 4;
253
		msg_bytes = 5;
254
		msg[3] = msg_bytes << 4;
255
		msg[4] = write_byte;
243
		radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
256 244
	}
257 245

  
258
	/* special handling for start/stop */
259
	if (mode & (MODE_I2C_START | MODE_I2C_STOP))
260
		msg[3] = 3 << 4;
261

  
262
	/* Set MOT bit for all but stop */
263
	if ((mode & MODE_I2C_STOP) == 0)
264
		msg[2] |= DP_AUX_I2C_MOT << 4;
265

  
266
	for (retry = 0; retry < 7; retry++) {
267
		ret = radeon_process_aux_ch(auxch,
268
					    msg, msg_bytes, reply, reply_bytes, 0, &ack);
269
		if (ret == -EBUSY)
270
			continue;
271
		else if (ret < 0) {
272
			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
273
			return ret;
274
		}
275

  
276
		switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
277
		case DP_AUX_NATIVE_REPLY_ACK:
278
			/* I2C-over-AUX Reply field is only valid
279
			 * when paired with AUX ACK.
280
			 */
281
			break;
282
		case DP_AUX_NATIVE_REPLY_NACK:
283
			DRM_DEBUG_KMS("aux_ch native nack\n");
284
			return -EREMOTEIO;
285
		case DP_AUX_NATIVE_REPLY_DEFER:
286
			DRM_DEBUG_KMS("aux_ch native defer\n");
287
			usleep_range(500, 600);
288
			continue;
289
		default:
290
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
291
			return -EREMOTEIO;
292
		}
293

  
294
		switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
295
		case DP_AUX_I2C_REPLY_ACK:
296
			if (mode == MODE_I2C_READ)
297
				*read_byte = reply[0];
298
			return (0);		/* XXX: why 0 and not msg size? */
299
		case DP_AUX_I2C_REPLY_NACK:
300
			DRM_DEBUG_KMS("aux_i2c nack\n");
301
			return -EREMOTEIO;
302
		case DP_AUX_I2C_REPLY_DEFER:
303
			DRM_DEBUG_KMS("aux_i2c defer\n");
304
			usleep_range(400, 500);
305
			break;
306
		default:
307
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
308
			return -EREMOTEIO;
309
		}
310
	}
246
	ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
247
	if (!ret)
248
		radeon_connector->ddc_bus->has_aux = true;
311 249

  
312
	DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
313
	return -EREMOTEIO;
250
	WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
314 251
}
315 252

  
316 253
/***** general DP utility functions *****/
......
318 255
#define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_LEVEL_3
319 256
#define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPH_LEVEL_3
320 257

  
321
static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
258
static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
322 259
				int lane_count,
323 260
				u8 train_set[4])
324 261
{
......
365 302
		return bpc * 3;
366 303
}
367 304

  
368
/* get the max pix clock supported by the link rate and lane num */
369
static int dp_get_max_dp_pix_clock(int link_rate,
370
				   int lane_num,
371
				   int bpp)
372
{
373
	return (link_rate * lane_num * 8) / bpp;
374
}
375

  
376 305
/***** radeon specific DP functions *****/
377 306

  
378
static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
379
				       u8 dpcd[DP_DPCD_SIZE])
380
{
381
	int max_link_rate;
382

  
383
	if (radeon_connector_is_dp12_capable(connector))
384
		max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
385
	else
386
		max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
387

  
388
	return max_link_rate;
389
}
390

  
391
/* First get the min lane# when low rate is used according to pixel clock
392
 * (prefer low rate), second check max lane# supported by DP panel,
393
 * if the max lane# < low rate lane# then use max lane# instead.
394
 */
395
static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
396
					u8 dpcd[DP_DPCD_SIZE],
397
					int pix_clock)
307
int radeon_dp_get_dp_link_config(struct drm_connector *connector,
308
				 const u8 dpcd[DP_DPCD_SIZE],
309
				 unsigned pix_clock,
310
				 unsigned *dp_lanes, unsigned *dp_rate)
398 311
{
399 312
	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
400
	int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
401
	int max_lane_num = drm_dp_max_lane_count(dpcd);
402
	int lane_num;
403
	int max_dp_pix_clock;
404

  
405
	for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
406
		max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
407
		if (pix_clock <= max_dp_pix_clock)
408
			break;
409
	}
410

  
411
	return lane_num;
412
}
413

  
414
static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
415
				       u8 dpcd[DP_DPCD_SIZE],
416
				       int pix_clock)
417
{
418
	int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
419
	int lane_num, max_pix_clock;
313
	static const unsigned link_rates[3] = { 162000, 270000, 540000 };
314
	unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
315
	unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
316
	unsigned lane_num, i, max_pix_clock;
420 317

  
421 318
	if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
422
	    ENCODER_OBJECT_ID_NUTMEG)
423
		return 270000;
424

  
425
	lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
426
	max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
427
	if (pix_clock <= max_pix_clock)
428
		return 162000;
429
	max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
430
	if (pix_clock <= max_pix_clock)
431
		return 270000;
432
	if (radeon_connector_is_dp12_capable(connector)) {
433
		max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
434
		if (pix_clock <= max_pix_clock)
435
			return 540000;
436
	}
319
	    ENCODER_OBJECT_ID_NUTMEG) {
320
		for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
321
			max_pix_clock = (lane_num * 270000 * 8) / bpp;
322
			if (max_pix_clock >= pix_clock) {
323
				*dp_lanes = lane_num;
324
				*dp_rate = 270000;
325
				return 0;
326
			}
327
		}
328
	} else {
329
		for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
330
			for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
331
				max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
332
				if (max_pix_clock >= pix_clock) {
333
					*dp_lanes = lane_num;
334
					*dp_rate = link_rates[i];
335
					return 0;
336
				}
337
			}
338
		}
339
 	}
437 340

  
438
	return radeon_dp_get_max_link_rate(connector, dpcd);
341
	return -EINVAL;
439 342
}
440 343

  
441 344
static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
......
458 361

  
459 362
u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
460 363
{
461
	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
462 364
	struct drm_device *dev = radeon_connector->base.dev;
463 365
	struct radeon_device *rdev = dev->dev_private;
464 366

  
465 367
	return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
466
					 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
368
					 radeon_connector->ddc_bus->rec.i2c_id, 0);
467 369
}
468 370

  
469 371
static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
......
474 376
	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
475 377
		return;
476 378

  
477
	if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_SINK_OUI, buf, 3) == 3)
379
	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
478 380
		DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
479 381
			      buf[0], buf[1], buf[2]);
480 382

  
481
	if (drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
383
	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
482 384
		DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
483 385
			      buf[0], buf[1], buf[2]);
484 386
}
......
487 389
{
488 390
	struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
489 391
	u8 msg[DP_DPCD_SIZE];
490
	int ret;
392
	int ret, i;
491 393

  
492 394
	char dpcd_hex_dump[DP_DPCD_SIZE * 3];
493 395

  
494
	ret = drm_dp_dpcd_read(&dig_connector->dp_i2c_bus->aux, DP_DPCD_REV, msg,
495
			       DP_DPCD_SIZE);
496
	if (ret > 0) {
497
		memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
498
		DRM_DEBUG_KMS("DPCD: %s\n", hexncpy(dig_connector->dpcd,
499
			      sizeof(dig_connector->dpcd),
500
			      dpcd_hex_dump, sizeof(dpcd_hex_dump), " "));
396
	for (i = 0; i < 7; i++) {
397
		ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
398
				       DP_DPCD_SIZE);
399
		if (ret == DP_DPCD_SIZE) {
400
			memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
401
			DRM_DEBUG_KMS("DPCD: %s\n", hexncpy(dig_connector->dpcd,
402
				      sizeof(dig_connector->dpcd),
403
				      dpcd_hex_dump, sizeof(dpcd_hex_dump), " "));
501 404

  
502
		radeon_dp_probe_oui(radeon_connector);
405
			radeon_dp_probe_oui(radeon_connector);
503 406

  
504
		return true;
407
			return true;
408
		}
505 409
	}
506 410
	dig_connector->dpcd[0] = 0;
507 411
	return false;
......
528 432

  
529 433
	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
530 434
		/* DP bridge chips */
531
		if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
435
		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
532 436
				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
533 437
			if (tmp & 1)
534 438
				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
......
540 444
		}
541 445
	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
542 446
		/* eDP */
543
		if (drm_dp_dpcd_readb(&dig_connector->dp_i2c_bus->aux,
447
		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
544 448
				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
545 449
			if (tmp & 1)
546 450
				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
......
555 459
{
556 460
	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
557 461
	struct radeon_connector_atom_dig *dig_connector;
462
	int ret;
558 463

  
559 464
	if (!radeon_connector->con_priv)
560 465
		return;
......
562 467

  
563 468
	if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
564 469
	    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
565
		dig_connector->dp_clock =
566
			radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
567
		dig_connector->dp_lane_count =
568
			radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
470
		ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
471
						   mode->clock,
472
						   &dig_connector->dp_lane_count,
473
						   &dig_connector->dp_clock);
474
		if (ret) {
475
			dig_connector->dp_clock = 0;
476
			dig_connector->dp_lane_count = 0;
477
		}
569 478
	}
570 479
}
571 480

  
......
574 483
{
575 484
	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
576 485
	struct radeon_connector_atom_dig *dig_connector;
577
	int dp_clock;
486
	unsigned dp_clock, dp_lanes;
487
	int ret;
578 488

  
579 489
	if ((mode->clock > 340000) &&
580 490
	    (!radeon_connector_is_dp12_capable(connector)))
......
584 494
		return MODE_CLOCK_HIGH;
585 495
	dig_connector = radeon_connector->con_priv;
586 496

  
587
	dp_clock =
588
		radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
497
	ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
498
					   mode->clock,
499
					   &dp_lanes,
500
					   &dp_clock);
501
	if (ret)
502
		return MODE_CLOCK_HIGH;
589 503

  
590 504
	if ((dp_clock == 540000) &&
591 505
	    (!radeon_connector_is_dp12_capable(connector)))
......
599 513
	u8 link_status[DP_LINK_STATUS_SIZE];
600 514
	struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
601 515

  
602
	if (drm_dp_dpcd_read_link_status(&dig->dp_i2c_bus->aux, link_status) <= 0)
516
	if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
517
	    <= 0)
603 518
		return false;
604 519
	if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
605 520
		return false;
......
619 534

  
620 535
	/* power up/down the sink */
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